remove pixel clock
This commit is contained in:
nino-porcino
parent
b7a1632485
commit
02cd9b5ecb
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@ -25,8 +25,7 @@
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module apple1(
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input reset, // reset
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input sys_clock, // system clock
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input pixel_clock, // 7 MHz pixel clock
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input sys_clock, // system clock
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input pixel_clken, // 7 MHz pixel clock
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input cpu_clken, // cpu clock enable
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@ -106,7 +105,7 @@ assign ram_wr = we & ram_cs;
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display display(
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.reset(reset),
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.pixel_clock(sys_clock),
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.sys_clock(sys_clock),
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.pixel_clken(pixel_clken),
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.cpu_clken(cpu_clken & display_cs),
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@ -4,20 +4,16 @@
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//
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//
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// TODO clean reset, reset_n
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// TODO take power reset
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// TODO take out cpu clock enable
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// TODO make ram work with clock enable
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// TODO load binary files into memory
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// TODO make it work with SDRAM
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// TODO make ram work with clock enable
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// TODO ram refresh lost cycles
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// TODO power on-off key ? (init ram)
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// TODO ram powerup initial values
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// TODO reset if pll not locked
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// TODO reorganize file structure
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// TODO support ACI interface for load and save
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// TODO special expansion boards: TMS9918, SID, AY?
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// TODO check diff with updated data_io.v and other modules
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// TODO osd menu yellow, why it doesn't work?
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// TODO keyboard: isolate ps2 keyboard from apple1
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// TODO keyboard: check ps2 clock
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// TODO keyboard: reset and cls key
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@ -25,7 +21,6 @@
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// TODO display: powerup values
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// TODO display: simplify rom font
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// TODO display: reduce to 512 bytes font
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// TODO display: use 7 MHz clock
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// TODO display: check parameters vs real apple1
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// TODO display: check cursor blinking
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@ -115,18 +110,17 @@ wire reset_button = status[0] | st_menu_reset | st_reset_switch | !pll_locked;
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wire pll_locked;
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wire pixel_clock; // the 14.31818 MHz clock
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wire clk_osd; // x2 clock for the OSD menu
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wire sdram_clock; // cpu x 7 x 8 for sdram.v interface
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wire sys_clock; // cpu x 7 x 8 system clock (sdram.v)
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wire osd_clock; // cpu x 7 x 2 for the OSD menu
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wire sdram_clock_ph; // cpu x 7 x 8 phase shifted -2.5 ns
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pll pll
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(
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.inclk0(CLOCK_27),
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.locked(pll_locked),
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.c0( clk_osd ), // x2 video clock for OSD menu
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.c1( pixel_clock ), // 7.15909 MHz (14.318180/2)
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.c2( sdram_clock ), // cpu x 7 x 8
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.c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu
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.c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v)
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.c3( sdram_clock_ph ) // cpu x 7 x 8 phase shifted -2.5 ns
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);
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@ -165,7 +159,7 @@ downloader
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.ROM_done ( ROM_loaded ),
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// external ram interface
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.clk ( sdram_clock ),
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.clk ( sys_clock ),
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.clk_ena ( cpu_clken ),
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.wr ( download_wr ),
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.addr ( download_addr ),
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@ -180,8 +174,8 @@ downloader
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// RAM
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ram ram(
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.clk (sdram_clock),
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.ena (cpu_clken ),
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.clk (sys_clock ),
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.ena (cpu_clken ), // fake does not work
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.address(sdram_addr[15:0]),
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.w_en (sdram_wr ),
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.din (sdram_din ),
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@ -226,7 +220,7 @@ assign LED = ~dummy;
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// WozMon ROM
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wire [7:0] rom_dout;
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rom_wozmon rom_wozmon(
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.clk(sdram_clock),
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.clk(sys_clock),
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.address(cpu_addr[7:0]),
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.dout(rom_dout)
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);
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@ -234,7 +228,7 @@ rom_wozmon rom_wozmon(
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// Basic ROM
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wire [7:0] basic_dout;
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rom_basic rom_basic(
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.clk(sdram_clock),
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.clk(sys_clock),
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.address(cpu_addr[11:0]),
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.dout(basic_dout)
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);
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@ -258,10 +252,9 @@ apple1 apple1
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(
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.reset(reset_button),
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.sys_clock(sdram_clock), // system clock
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.pixel_clock(pixel_clock), // pixel clock 7 Mhz
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.cpu_clken(cpu_clken), // CPU clock enable
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.pixel_clken(pixel_clken), // pixel clock enable
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.sys_clock ( sys_clock ), // system clock
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.cpu_clken ( cpu_clken ), // CPU clock enable
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.pixel_clken ( pixel_clken ), // pixel clock enable
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// RAM interface
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.ram_addr (cpu_addr),
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@ -282,14 +275,22 @@ apple1 apple1
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.vga_cls() // clear screen button (not connected yet)
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @mist_video ************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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mist_video
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#(
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.COLOR_DEPTH(1), // 1 bit color depth
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.OSD_AUTO_CE(1) // OSD autodetects clock enable
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.OSD_AUTO_CE(1), // OSD autodetects clock enable
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.OSD_COLOR(3'b110) // yellow menu color
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)
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mist_video
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(
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.clk_sys(clk_osd), // OSD needs 2x the VDP clock for the scandoubler
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.clk_sys(osd_clock), // OSD needs 2x the VDP clock for the scandoubler
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// OSD SPI interface
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.SPI_DI(SPI_DI),
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@ -321,6 +322,12 @@ mist_video
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.VGA_HS(VGA_HS),
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @user_io ***************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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user_io
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#(
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.STRLEN(conf_str_len)
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@ -329,7 +336,7 @@ user_io
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user_io (
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.conf_str (CONF_STR ),
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.clk_sys (sdram_clock ),
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.clk_sys (sys_clock ),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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@ -356,7 +363,7 @@ user_io (
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// SDRAM control signals
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assign SDRAM_CKE = 1'b1;
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assign SDRAM_CLK = sdram_clock_ph;
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assign SDRAM_CLK = sdram_clock_ph; // same as sys_clock but with -2.5 ns phase
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/*
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wire [24:0] sdram_addr;
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@ -421,7 +428,7 @@ wire cpu_clken; // provides the cpu clock enable signal derived from main clo
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wire pixel_clken; // provides the cpu clock enable signal derived from main clock
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clock clock(
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.sys_clock ( sdram_clock ), // input: main clock
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.sys_clock ( sys_clock ), // input: main clock
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.reset ( reset_button ), // input: reset signal
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.cpu_clken ( cpu_clken ), // output: cpu clock enable
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10
rtl/clock.v
10
rtl/clock.v
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@ -4,8 +4,8 @@ module clock
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input sys_clock, // master clock at cpu x 7 x 8
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input reset, // reset
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output reg cpu_clken, // 1MHz clock enable for the CPU
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output reg pixel_clken // 7MHz clock enable for the display
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output cpu_clken, // 1MHz clock enable for the CPU
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output pixel_clken // 7MHz clock enable for the display
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);
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localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz
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@ -27,10 +27,10 @@ localparam PIXEL_DIVISOR = 8; // (sys_clock / PIXEL_DIVISOR) = 7 MHz
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if (counter_pixel == (PIXEL_DIVISOR-1)) counter_pixel <= 0;
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else counter_pixel <= counter_pixel + 1;
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cpu_clken <= counter_cpu == 0;
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pixel_clken <= counter_pixel == 0;
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end
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end
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assign cpu_clken = counter_cpu == 0;
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assign pixel_clken = counter_pixel == 0;
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endmodule
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@ -1,10 +1,9 @@
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module display (
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input reset, // active high reset signal
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input pixel_clock, // 7 MHz clock signal
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input pixel_clken, // pixel clock enable
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input cpu_clken, // clock cpu_clken strobe,
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input sys_clock, // system clock
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input pixel_clken, // pixel clock enable
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input cpu_clken, // cpu clock enable
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input clr_screen, // clear screen button
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@ -73,7 +72,7 @@ module display (
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wire v_active = (v_cnt >= vbp && v_cnt < vfp);
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// horizontal and vertical counters
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always @(posedge pixel_clock or posedge reset) begin
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always @(posedge sys_clock or posedge reset) begin
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if (reset) begin
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h_cnt <= 10'd0;
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v_cnt <= 10'd0;
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@ -112,7 +111,7 @@ module display (
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// Character ROM
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font_rom font_rom(
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.clk(pixel_clock),
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.clk(sys_clock),
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.character(font_char),
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.pixel(font_pixel),
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.line(font_line),
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@ -123,7 +122,7 @@ module display (
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// Video RAM
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vram vram(
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.clk(pixel_clock),
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.clk(sys_clock),
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.read_addr(vram_r_addr),
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.write_addr(vram_w_addr),
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.r_en(h_active),
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@ -135,7 +134,7 @@ module display (
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//////////////////////////////////////////////////////////////////////////
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// Video Signal Generation
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always @(posedge pixel_clock or posedge reset) begin
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always @(posedge sys_clock or posedge reset) begin
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if (reset) begin
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vram_h_addr <= 0;
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vram_v_addr <= 0;
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@ -162,7 +161,7 @@ module display (
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reg blink;
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reg [22:0] blink_div;
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always @(posedge pixel_clock or posedge reset)
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always @(posedge sys_clock or posedge reset)
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begin
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if (reset)
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blink_div <= 0;
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@ -200,7 +199,7 @@ module display (
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assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]};
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always @(posedge pixel_clock or posedge reset)
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always @(posedge sys_clock or posedge reset)
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begin
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if (reset)
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begin
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