Apple-1-HW/Apple1_MiST
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remove pixel clock

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This commit is contained in:
nino-porcino 2022-01-02 22:20:44 +01:00
parent b7a1632485
commit 02cd9b5ecb
4 changed files with 50 additions and 45 deletions
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3
rtl/apple1.v
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@ -26,7 +26,6 @@ module apple1(
input reset, // reset input reset, // reset
input sys_clock, // system clock input sys_clock, // system clock
input pixel_clock, // 7 MHz pixel clock
input pixel_clken, // 7 MHz pixel clock input pixel_clken, // 7 MHz pixel clock
input cpu_clken, // cpu clock enable input cpu_clken, // cpu clock enable
@ -106,7 +105,7 @@ assign ram_wr = we & ram_cs;
display display( display display(
.reset(reset), .reset(reset),
.pixel_clock(sys_clock), .sys_clock(sys_clock),
.pixel_clken(pixel_clken), .pixel_clken(pixel_clken),
.cpu_clken(cpu_clken & display_cs), .cpu_clken(cpu_clken & display_cs),

61
rtl/apple1_mist.sv
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@ -4,20 +4,16 @@
// //
// //
// TODO clean reset, reset_n
// TODO take power reset
// TODO take out cpu clock enable
// TODO make ram work with clock enable
// TODO load binary files into memory
// TODO make it work with SDRAM // TODO make it work with SDRAM
// TODO make ram work with clock enable
// TODO ram refresh lost cycles // TODO ram refresh lost cycles
// TODO power on-off key ? (init ram) // TODO power on-off key ? (init ram)
// TODO ram powerup initial values // TODO ram powerup initial values
// TODO reset if pll not locked
// TODO reorganize file structure // TODO reorganize file structure
// TODO support ACI interface for load and save // TODO support ACI interface for load and save
// TODO special expansion boards: TMS9918, SID, AY? // TODO special expansion boards: TMS9918, SID, AY?
// TODO check diff with updated data_io.v and other modules // TODO check diff with updated data_io.v and other modules
// TODO osd menu yellow, why it doesn't work?
// TODO keyboard: isolate ps2 keyboard from apple1 // TODO keyboard: isolate ps2 keyboard from apple1
// TODO keyboard: check ps2 clock // TODO keyboard: check ps2 clock
// TODO keyboard: reset and cls key // TODO keyboard: reset and cls key
@ -25,7 +21,6 @@
// TODO display: powerup values // TODO display: powerup values
// TODO display: simplify rom font // TODO display: simplify rom font
// TODO display: reduce to 512 bytes font // TODO display: reduce to 512 bytes font
// TODO display: use 7 MHz clock
// TODO display: check parameters vs real apple1 // TODO display: check parameters vs real apple1
// TODO display: check cursor blinking // TODO display: check cursor blinking
@ -115,18 +110,17 @@ wire reset_button = status[0] | st_menu_reset | st_reset_switch | !pll_locked;
wire pll_locked; wire pll_locked;
wire pixel_clock; // the 14.31818 MHz clock wire sys_clock; // cpu x 7 x 8 system clock (sdram.v)
wire clk_osd; // x2 clock for the OSD menu wire osd_clock; // cpu x 7 x 2 for the OSD menu
wire sdram_clock; // cpu x 7 x 8 for sdram.v interface
wire sdram_clock_ph; // cpu x 7 x 8 phase shifted -2.5 ns wire sdram_clock_ph; // cpu x 7 x 8 phase shifted -2.5 ns
pll pll pll pll
( (
.inclk0(CLOCK_27), .inclk0(CLOCK_27),
.locked(pll_locked), .locked(pll_locked),
.c0( clk_osd ), // x2 video clock for OSD menu
.c1( pixel_clock ), // 7.15909 MHz (14.318180/2) .c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu
.c2( sdram_clock ), // cpu x 7 x 8 .c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v)
.c3( sdram_clock_ph ) // cpu x 7 x 8 phase shifted -2.5 ns .c3( sdram_clock_ph ) // cpu x 7 x 8 phase shifted -2.5 ns
); );
@ -165,7 +159,7 @@ downloader
.ROM_done ( ROM_loaded ), .ROM_done ( ROM_loaded ),
// external ram interface // external ram interface
.clk ( sdram_clock ), .clk ( sys_clock ),
.clk_ena ( cpu_clken ), .clk_ena ( cpu_clken ),
.wr ( download_wr ), .wr ( download_wr ),
.addr ( download_addr ), .addr ( download_addr ),
@ -180,8 +174,8 @@ downloader
// RAM // RAM
ram ram( ram ram(
.clk (sdram_clock), .clk (sys_clock ),
.ena (cpu_clken ), .ena (cpu_clken ), // fake does not work
.address(sdram_addr[15:0]), .address(sdram_addr[15:0]),
.w_en (sdram_wr ), .w_en (sdram_wr ),
.din (sdram_din ), .din (sdram_din ),
@ -226,7 +220,7 @@ assign LED = ~dummy;
// WozMon ROM // WozMon ROM
wire [7:0] rom_dout; wire [7:0] rom_dout;
rom_wozmon rom_wozmon( rom_wozmon rom_wozmon(
.clk(sdram_clock), .clk(sys_clock),
.address(cpu_addr[7:0]), .address(cpu_addr[7:0]),
.dout(rom_dout) .dout(rom_dout)
); );
@ -234,7 +228,7 @@ rom_wozmon rom_wozmon(
// Basic ROM // Basic ROM
wire [7:0] basic_dout; wire [7:0] basic_dout;
rom_basic rom_basic( rom_basic rom_basic(
.clk(sdram_clock), .clk(sys_clock),
.address(cpu_addr[11:0]), .address(cpu_addr[11:0]),
.dout(basic_dout) .dout(basic_dout)
); );
@ -258,10 +252,9 @@ apple1 apple1
( (
.reset(reset_button), .reset(reset_button),
.sys_clock(sdram_clock), // system clock .sys_clock ( sys_clock ), // system clock
.pixel_clock(pixel_clock), // pixel clock 7 Mhz .cpu_clken ( cpu_clken ), // CPU clock enable
.cpu_clken(cpu_clken), // CPU clock enable .pixel_clken ( pixel_clken ), // pixel clock enable
.pixel_clken(pixel_clken), // pixel clock enable
// RAM interface // RAM interface
.ram_addr (cpu_addr), .ram_addr (cpu_addr),
@ -282,14 +275,22 @@ apple1 apple1
.vga_cls() // clear screen button (not connected yet) .vga_cls() // clear screen button (not connected yet)
); );
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @mist_video ************************************/
/******************************************************************************************/
/******************************************************************************************/
mist_video mist_video
#( #(
.COLOR_DEPTH(1), // 1 bit color depth .COLOR_DEPTH(1), // 1 bit color depth
.OSD_AUTO_CE(1) // OSD autodetects clock enable .OSD_AUTO_CE(1), // OSD autodetects clock enable
.OSD_COLOR(3'b110) // yellow menu color
) )
mist_video mist_video
( (
.clk_sys(clk_osd), // OSD needs 2x the VDP clock for the scandoubler .clk_sys(osd_clock), // OSD needs 2x the VDP clock for the scandoubler
// OSD SPI interface // OSD SPI interface
.SPI_DI(SPI_DI), .SPI_DI(SPI_DI),
@ -321,6 +322,12 @@ mist_video
.VGA_HS(VGA_HS), .VGA_HS(VGA_HS),
); );
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @user_io ***************************************/
/******************************************************************************************/
/******************************************************************************************/
user_io user_io
#( #(
.STRLEN(conf_str_len) .STRLEN(conf_str_len)
@ -329,7 +336,7 @@ user_io
user_io ( user_io (
.conf_str (CONF_STR ), .conf_str (CONF_STR ),
.clk_sys (sdram_clock ), .clk_sys (sys_clock ),
.SPI_CLK (SPI_SCK ), .SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ), .SPI_SS_IO (CONF_DATA0 ),
@ -356,7 +363,7 @@ user_io (
// SDRAM control signals // SDRAM control signals
assign SDRAM_CKE = 1'b1; assign SDRAM_CKE = 1'b1;
assign SDRAM_CLK = sdram_clock_ph; assign SDRAM_CLK = sdram_clock_ph; // same as sys_clock but with -2.5 ns phase
/* /*
wire [24:0] sdram_addr; wire [24:0] sdram_addr;
@ -421,7 +428,7 @@ wire cpu_clken; // provides the cpu clock enable signal derived from main clo
wire pixel_clken; // provides the cpu clock enable signal derived from main clock wire pixel_clken; // provides the cpu clock enable signal derived from main clock
clock clock( clock clock(
.sys_clock ( sdram_clock ), // input: main clock .sys_clock ( sys_clock ), // input: main clock
.reset ( reset_button ), // input: reset signal .reset ( reset_button ), // input: reset signal
.cpu_clken ( cpu_clken ), // output: cpu clock enable .cpu_clken ( cpu_clken ), // output: cpu clock enable

10
rtl/clock.v
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@ -4,8 +4,8 @@ module clock
input sys_clock, // master clock at cpu x 7 x 8 input sys_clock, // master clock at cpu x 7 x 8
input reset, // reset input reset, // reset
output reg cpu_clken, // 1MHz clock enable for the CPU output cpu_clken, // 1MHz clock enable for the CPU
output reg pixel_clken // 7MHz clock enable for the display output pixel_clken // 7MHz clock enable for the display
); );
localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz
@ -27,10 +27,10 @@ localparam PIXEL_DIVISOR = 8; // (sys_clock / PIXEL_DIVISOR) = 7 MHz
if (counter_pixel == (PIXEL_DIVISOR-1)) counter_pixel <= 0; if (counter_pixel == (PIXEL_DIVISOR-1)) counter_pixel <= 0;
else counter_pixel <= counter_pixel + 1; else counter_pixel <= counter_pixel + 1;
cpu_clken <= counter_cpu == 0;
pixel_clken <= counter_pixel == 0;
end end
end end
assign cpu_clken = counter_cpu == 0;
assign pixel_clken = counter_pixel == 0;
endmodule endmodule

17
rtl/display.v
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@ -1,10 +1,9 @@
module display ( module display (
input reset, // active high reset signal input reset, // active high reset signal
input pixel_clock, // 7 MHz clock signal input sys_clock, // system clock
input pixel_clken, // pixel clock enable input pixel_clken, // pixel clock enable
input cpu_clken, // cpu clock enable
input cpu_clken, // clock cpu_clken strobe,
input clr_screen, // clear screen button input clr_screen, // clear screen button
@ -73,7 +72,7 @@ module display (
wire v_active = (v_cnt >= vbp && v_cnt < vfp); wire v_active = (v_cnt >= vbp && v_cnt < vfp);
// horizontal and vertical counters // horizontal and vertical counters
always @(posedge pixel_clock or posedge reset) begin always @(posedge sys_clock or posedge reset) begin
if (reset) begin if (reset) begin
h_cnt <= 10'd0; h_cnt <= 10'd0;
v_cnt <= 10'd0; v_cnt <= 10'd0;
@ -112,7 +111,7 @@ module display (
// Character ROM // Character ROM
font_rom font_rom( font_rom font_rom(
.clk(pixel_clock), .clk(sys_clock),
.character(font_char), .character(font_char),
.pixel(font_pixel), .pixel(font_pixel),
.line(font_line), .line(font_line),
@ -123,7 +122,7 @@ module display (
// Video RAM // Video RAM
vram vram( vram vram(
.clk(pixel_clock), .clk(sys_clock),
.read_addr(vram_r_addr), .read_addr(vram_r_addr),
.write_addr(vram_w_addr), .write_addr(vram_w_addr),
.r_en(h_active), .r_en(h_active),
@ -135,7 +134,7 @@ module display (
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Video Signal Generation // Video Signal Generation
always @(posedge pixel_clock or posedge reset) begin always @(posedge sys_clock or posedge reset) begin
if (reset) begin if (reset) begin
vram_h_addr <= 0; vram_h_addr <= 0;
vram_v_addr <= 0; vram_v_addr <= 0;
@ -162,7 +161,7 @@ module display (
reg blink; reg blink;
reg [22:0] blink_div; reg [22:0] blink_div;
always @(posedge pixel_clock or posedge reset) always @(posedge sys_clock or posedge reset)
begin begin
if (reset) if (reset)
blink_div <= 0; blink_div <= 0;
@ -200,7 +199,7 @@ module display (
assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]}; assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]};
always @(posedge pixel_clock or posedge reset) always @(posedge sys_clock or posedge reset)
begin begin
if (reset) if (reset)
begin begin