diff --git a/rtl/aci.v b/rtl/aci.v
index ed10630..b460ea3 100644
--- a/rtl/aci.v
+++ b/rtl/aci.v
@@ -7,7 +7,7 @@ module ACI (
    input clk,              // clock signal
    input cpu_clken,        // CPU clock enable      
 
-   input [15:0] address,   // address bus   
+   input [15:0] addr,      // address bus   
    output reg [7:0] dout,  // 8-bit data bus (output)
 
    output reg tape_out,    // tape output
@@ -19,16 +19,16 @@ module ACI (
    initial
       $readmemh("roms/aci.hex", rom_data, 0, 255);
 
-	wire io_range  = address >= 16'hC000 && address <= 16'hC0FF;
+	wire io_range = addr >= 16'hC000 && addr <= 16'hC0FF;
 	
-   wire [7:0] read_address = io_range ? { address[7:1], address[0] & tape_in } : address[7:0];
+   wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & tape_in } : addr[7:0];
 		
    always @(posedge clk) begin
 
       if(cpu_clken & io_range)
          tape_out <= ~tape_out;
 
-      dout <= rom_data[read_address];
+      dout <= rom_data[read_addr];
    end
 
 endmodule
diff --git a/rtl/apple1_mist.sv b/rtl/apple1_mist.sv
index d3b3baa..1b7b075 100644
--- a/rtl/apple1_mist.sv
+++ b/rtl/apple1_mist.sv
@@ -224,7 +224,7 @@ wire CASOUT;
 ACI ACI(
   .clk(sys_clock),
   .cpu_clken(cpu_clken),
-  .address(sdram_addr[15:0]),
+  .addr(sdram_addr[15:0]),
   .dout(aci_dout),
   .tape_in(CASIN),
   .tape_out(CASOUT),