From 21c8cfa965ae95cff3efe51018edbc02f88ddb51 Mon Sep 17 00:00:00 2001 From: nino-porcino Date: Sun, 2 Jan 2022 11:57:11 +0100 Subject: [PATCH] use 7Mhz clock in display --- rtl/apple1.v | 16 +++++++++------- rtl/apple1_mist.sv | 23 ++++++++++++++--------- rtl/clock.v | 6 +++--- rtl/display.v | 37 ++++++++++++++++++------------------- rtl/font_rom.v | 4 ++-- rtl/pll.v | 16 ++++++++-------- rtl/ps2keyboard.v | 10 +++++----- rtl/pwr_reset.v | 4 ++-- rtl/ram.v | 7 ++++--- 9 files changed, 65 insertions(+), 58 deletions(-) diff --git a/rtl/apple1.v b/rtl/apple1.v index 5ad8012..bcf7e51 100644 --- a/rtl/apple1.v +++ b/rtl/apple1.v @@ -23,8 +23,10 @@ // module apple1( - input clk14, // 14 MHz master clock + input clk7, // 7 MHz master clock input rst_n, // active low synchronous reset (needed for simulation) + + output cpu_clken, // cpu clock enable // RAM interface output [15:0] ram_addr, @@ -62,9 +64,9 @@ assign ram_wr = we & ram_cs; ////////////////////////////////////////////////////////////////////////// // Clocks - wire cpu_clken; + //wire cpu_clken; clock clock( - .clk14(clk14), + .clk7(clk7), .rst_n(rst_n), .cpu_clken(cpu_clken) ); @@ -74,7 +76,7 @@ assign ram_wr = we & ram_cs; wire rst; pwr_reset pwr_reset( - .clk14(clk14), + .clk7(clk7), .rst_n(rst_n), .enable(cpu_clken), .rst(rst) @@ -84,7 +86,7 @@ assign ram_wr = we & ram_cs; // 6502 arlet_6502 arlet_6502( - .clk (clk14), + .clk (clk7), .enable (cpu_clken), .rst (rst), .ab (addr), @@ -115,7 +117,7 @@ assign ram_wr = we & ram_cs; // PS/2 keyboard interface wire [7:0] ps2_dout; ps2keyboard keyboard( - .clk14(clk14), + .clk7(clk7), .rst(rst), .key_clk(ps2_clk), .key_din(ps2_din), @@ -125,7 +127,7 @@ assign ram_wr = we & ram_cs; ); display display( - .clk(clk14), + .clk(clk7), .enable(display_cs & cpu_clken), .rst(rst), diff --git a/rtl/apple1_mist.sv b/rtl/apple1_mist.sv index 4ab4907..8fe9de4 100644 --- a/rtl/apple1_mist.sv +++ b/rtl/apple1_mist.sv @@ -20,6 +20,7 @@ // TODO keyboard: reset and cls key // TODO keyboard: make a true ascii keyboard // TODO display: powerup values +// TODO display: simplify rom font // TODO display: reduce to 512 bytes font // TODO display: use 7 MHz clock // TODO display: check parameters vs real apple1 @@ -86,7 +87,7 @@ localparam conf_str_len = $size(CONF_STR)>>3; wire st_reset_switch = buttons[1]; wire st_menu_reset = status[6]; -wire clk14; // the 14.31818 MHz clock +wire clk7; // the 14.31818 MHz clock wire clk_osd; // x2 clock for the OSD menu wire r, g, b; wire hs, vs; @@ -117,7 +118,7 @@ pll pll .inclk0(CLOCK_27), .locked(pll_locked), .c0(clk_osd), // x2 clock for OSD menu - .c1(clk14) // 14.31818 MHz system clock + .c1(clk7) // 14.318180/2 = 7.15909 MHz system clock /* .c2 ( sys_clock ), // cpu x 8 @@ -160,8 +161,8 @@ downloader .ROM_done ( ROM_loaded ), // external ram interface - .clk ( clk14 ), - .clk_ena ( 1 ), + .clk ( clk7 ), + .clk_ena ( cpu_clken ), .wr ( download_wr ), .addr ( download_addr ), .data ( download_data ) @@ -175,7 +176,8 @@ downloader // RAM ram ram( - .clk (clk14 ), + .clk (clk7 ), + .ena (cpu_clken ), .address(sdram_addr[15:0]), .w_en (sdram_wr ), .din (sdram_din ), @@ -221,7 +223,7 @@ assign LED = ~dummy; // WozMon ROM wire [7:0] rom_dout; rom_wozmon rom_wozmon( - .clk(clk14), + .clk(clk7), .address(cpu_addr[7:0]), .dout(rom_dout) ); @@ -229,7 +231,7 @@ rom_wozmon rom_wozmon( // Basic ROM wire [7:0] basic_dout; rom_basic rom_basic( - .clk(clk14), + .clk(clk7), .address(cpu_addr[11:0]), .dout(basic_dout) ); @@ -249,12 +251,15 @@ wire [7:0] bus_dout = basic_cs ? basic_dout : ram_cs ? sdram_dout : 8'b0; +wire cpu_clken; apple1 apple1 ( - .clk14(clk14), + .clk7(clk7), .rst_n(~reset_button), + .cpu_clken(cpu_clken), // apple1 outputs the CPU clock enable + // RAM interface .ram_addr (cpu_addr), .ram_din (cpu_dout), @@ -321,7 +326,7 @@ user_io user_io ( .conf_str (CONF_STR ), - .clk_sys (clk14 ), + .clk_sys (clk7 ), .SPI_CLK (SPI_SCK ), .SPI_SS_IO (CONF_DATA0 ), diff --git a/rtl/clock.v b/rtl/clock.v index 715112c..520930d 100644 --- a/rtl/clock.v +++ b/rtl/clock.v @@ -25,7 +25,7 @@ module clock ( - input clk14, // 14MHz clock master clock + input clk7, // 7MHz clock master clock input rst_n, // active low synchronous reset // Clock enables @@ -42,9 +42,9 @@ module clock // reg [4:0] clk_div; - always @(posedge clk14) + always @(posedge clk7) begin - if ((clk_div == 14) || (rst_n == 1'b0)) + if ((clk_div == 7) || (rst_n == 1'b0)) clk_div <= 0; else clk_div <= clk_div + 1'b1; diff --git a/rtl/display.v b/rtl/display.v index 43dcac4..af56cac 100644 --- a/rtl/display.v +++ b/rtl/display.v @@ -1,5 +1,5 @@ module display ( - input clk, // 14 MHz clock signal + input clk, // 7 MHz clock signal input rst, // active high reset signal input enable, // clock enable strobe, @@ -22,10 +22,10 @@ module display ( // Registers and Parameters // video structure constants - parameter h_pixels = 910; // horizontal pixels per line - parameter h_pulse = 65; // hsync pulse length - parameter hbp = 208; // end of horizontal back porch - parameter hfp = 848; // beginning of horizontal front porch + parameter h_pixels = 455; // 910; // horizontal pixels per line + parameter h_pulse = 32; // 65; // hsync pulse length + parameter hbp = 104; // 208; // end of horizontal back porch + parameter hfp = 424; // 848; // beginning of horizontal front porch parameter v_lines = 262; // vertical lines per frame parameter v_pulse = 2; // vsync pulse length parameter vbp = 42; // end of vertical back porch @@ -34,8 +34,8 @@ module display ( // registers for storing the horizontal & vertical counters reg [9:0] h_cnt; // horizontal counter reg [9:0] v_cnt; // vertical counter - reg [4:0] v_dot; // vertical counter within character matrix (0-7) - wire [3:0] h_dot; // horizontal counter within character matrix (0-7) + reg [2:0] v_dot; // vertical counter within character matrix (0-7) + wire [2:0] h_dot; // horizontal counter within character matrix (0-7) // hardware cursor registers wire [10:0] cursor; @@ -58,7 +58,7 @@ module display ( // font rom registers wire [5:0] font_char; - wire [3:0] font_pixel; + wire [2:0] font_pixel; wire [4:0] font_line; wire font_out; @@ -101,9 +101,8 @@ module display ( end end end - - // count 16 pixels, so 640px / 16 = 40 characters - assign h_dot = h_active ? h_cnt[3:0] : 4'd0; + + assign h_dot = h_active ? h_cnt[2:0] : 0; ////////////////////////////////////////////////////////////////////////// // Character ROM @@ -134,21 +133,21 @@ module display ( always @(posedge clk or posedge rst) begin if (rst) begin - vram_h_addr <= 'd0; - vram_v_addr <= 'd0; + vram_h_addr <= 0; + vram_v_addr <= 0; end else begin // start the pipeline for reading vram and font details // 3 pixel clock cycles early - if (h_dot == 4'hC) - vram_h_addr <= vram_h_addr + 'd1; + if (h_dot == 6) + vram_h_addr <= vram_h_addr + 1; // advance to next row when last display line is reached for row - if (v_dot == 5'd7 && h_cnt == 10'd0) - vram_v_addr <= vram_v_addr + 'd1; + if (v_dot == 7 && h_cnt == 0) + vram_v_addr <= vram_v_addr + 1; // clear the address registers if we're not in visible area - if (~h_active) vram_h_addr <= 'd0; + if (~h_active) vram_h_addr <= 0; if (~v_active) vram_v_addr <= vram_start_addr; end end @@ -179,7 +178,7 @@ module display ( assign vram_r_addr = {vram_v_addr, vram_h_addr}; assign font_char = (vram_r_addr != cursor) ? vram_dout : (blink) ? 6'd0 : 6'd32; - assign font_pixel = h_dot + 1; // offset by one to get pixel into right cycle, + assign font_pixel = h_dot; // offset by one to get pixel into right cycle, // font output one pixel clk behind assign font_line = v_dot * 2 + 4; diff --git a/rtl/font_rom.v b/rtl/font_rom.v index b6bddd6..2384b1f 100644 --- a/rtl/font_rom.v +++ b/rtl/font_rom.v @@ -24,7 +24,7 @@ module font_rom ( input clk, // clock signal input [5:0] character, // address bus - input [3:0] pixel, // address of the pixel to output + input [2:0] pixel, // address of the pixel to output input [4:0] line, // address of the line to output output reg out // single pixel from address and pixel pos ); @@ -54,7 +54,7 @@ module font_rom ( begin romout = rom[(character * 10) + {2'd0, line_ptr}]; - out <= romout[pixel[3:1]]; + out <= romout[pixel]; end endmodule diff --git a/rtl/pll.v b/rtl/pll.v index c352f56..ec7560f 100644 --- a/rtl/pll.v +++ b/rtl/pll.v @@ -107,11 +107,11 @@ module pll ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 675000, + altpll_component.clk0_divide_by = 1350000, altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 715909, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 1350000, + altpll_component.clk1_divide_by = 2700000, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 715909, altpll_component.clk1_phase_shift = "0", @@ -192,8 +192,8 @@ endmodule // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636360" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.318180" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318180" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.159090" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -221,8 +221,8 @@ endmodule // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63636000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31818000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.31818000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.15909000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" @@ -268,11 +268,11 @@ endmodule // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "675000" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1350000" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "715909" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1350000" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2700000" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "715909" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" diff --git a/rtl/ps2keyboard.v b/rtl/ps2keyboard.v index 2d3ff37..20a4873 100644 --- a/rtl/ps2keyboard.v +++ b/rtl/ps2keyboard.v @@ -22,7 +22,7 @@ // module ps2keyboard ( - input clk14, // 25MHz clock + input clk7, // 25MHz clock input rst, // active high reset // I/O interface to keyboard @@ -43,7 +43,7 @@ module ps2keyboard ( reg [7:0] rx; // scancode receive buffer // wire ps2_clkdb; // debounced PS/2 clock signal - reg prev_ps2_clkdb; // previous clock state (in clk14 domain) + reg prev_ps2_clkdb; // previous clock state (in clk7 domain) // keyboard translation signals reg [7:0] ascii; // ASCII code of received character @@ -54,13 +54,13 @@ module ps2keyboard ( // debounce ps2clk_debounce // ( - // .clk14(clk14), + // .clk7(clk7), // .rst(rst), // .sig_in(key_clk), // .sig_out(ps2_clkdb) // ); - always @(posedge clk14 or posedge rst) + always @(posedge clk7 or posedge rst) begin if (rst) begin @@ -112,7 +112,7 @@ module ps2keyboard ( localparam S_KEYE0 = 3'b010; // extended key state localparam S_KEYE0F0 = 3'b011; // extended release state - always @(posedge clk14 or posedge rst) + always @(posedge clk7 or posedge rst) begin if (rst) begin diff --git a/rtl/pwr_reset.v b/rtl/pwr_reset.v index 1d85c14..29a4ec4 100644 --- a/rtl/pwr_reset.v +++ b/rtl/pwr_reset.v @@ -24,7 +24,7 @@ // module pwr_reset( - input clk14, // 14Mhz master clock + input clk7, // 7Mhz master clock input rst_n, // active low synchronous reset input enable, // clock enable output rst // active high synchronous system reset @@ -34,7 +34,7 @@ module pwr_reset( reg [5:0] reset_cnt; wire pwr_up_flag = &reset_cnt; - always @(posedge clk14) + always @(posedge clk7) begin if (rst_n == 1'b0) begin diff --git a/rtl/ram.v b/rtl/ram.v index 2192f48..3ee2375 100644 --- a/rtl/ram.v +++ b/rtl/ram.v @@ -24,6 +24,7 @@ module ram ( input clk, // clock signal + input ena, input [15:0] address, // address bus input w_en, // active high write enable strobe input [7:0] din, // 8-bit data bus (input) @@ -36,9 +37,9 @@ module ram ( // $readmemh("roms/ram.hex", ram_data, 0, 8191); always @(posedge clk) - begin - dout <= ram_data[address]; - if (w_en) ram_data[address] <= din; + begin + dout <= ram_data[address]; + if (w_en) ram_data[address] <= din; end endmodule