make ram module variable in size

apple-one.qsf

@@ -154,6 +154,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 
 # end ENTITY(apple1_mist)
 # -----------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/downloader.sv
 set_global_assignment -name VERILOG_FILE rtl/display.v
 set_global_assignment -name VERILOG_FILE rtl/sdram.v
@@ -175,7 +176,6 @@ set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v
 set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v
 set_global_assignment -name VERILOG_FILE rtl/apple1.v
 set_global_assignment -name VERILOG_FILE rtl/clock.v
-set_global_assignment -name VERILOG_FILE rtl/ram.v
 set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
 set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v
 set_global_assignment -name VERILOG_FILE rtl/vram.v

rtl/ram.sv

@@ -22,24 +22,26 @@
 // Date.......: 26-1-2018
 //
 
+
 module ram (
-    input clk,              // clock signal
-	 input ena,
+    input clk,              // clock signal	 	
     input [15:0] address,   // address bus
     input w_en,             // active high write enable strobe
     input [7:0] din,        // 8-bit data bus (input)
     output reg [7:0] dout   // 8-bit data bus (output)
 );
 
-    reg [7:0] ram_data[0:49151];
+    parameter SIZE = 49152;
+
+    reg [7:0] ram_data[0:SIZE-1];
 
     //initial
     //    $readmemh("roms/ram.hex", ram_data, 0, 8191);
-
+	 	 
     always @(posedge clk)
-    begin		  
-		 dout <= ram_data[address];
-       if (w_en) ram_data[address] <= din;		  
+    begin		       
+		dout <= ram_data[address];
+		if (w_en) ram_data[address] <= din;		  		 
     end
 
 endmodule