Apple-1-HW/Apple1_MiST
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make ram module variable in size

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nino-porcino 2022-01-05 18:23:14 +01:00
parent 5d7bd5d14e
commit 2ed47e3d64
2 changed files with 10 additions and 8 deletions
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2
apple-one.qsf
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@ -154,6 +154,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# end ENTITY(apple1_mist) # end ENTITY(apple1_mist)
# ----------------------- # -----------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/downloader.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/downloader.sv
set_global_assignment -name VERILOG_FILE rtl/display.v set_global_assignment -name VERILOG_FILE rtl/display.v
set_global_assignment -name VERILOG_FILE rtl/sdram.v set_global_assignment -name VERILOG_FILE rtl/sdram.v
@ -175,7 +176,6 @@ set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v
set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v
set_global_assignment -name VERILOG_FILE rtl/apple1.v set_global_assignment -name VERILOG_FILE rtl/apple1.v
set_global_assignment -name VERILOG_FILE rtl/clock.v set_global_assignment -name VERILOG_FILE rtl/clock.v
set_global_assignment -name VERILOG_FILE rtl/ram.v
set_global_assignment -name VERILOG_FILE rtl/rom_basic.v set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v
set_global_assignment -name VERILOG_FILE rtl/vram.v set_global_assignment -name VERILOG_FILE rtl/vram.v

10
rtl/ram.v → rtl/ram.sv
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@ -22,24 +22,26 @@
// Date.......: 26-1-2018 // Date.......: 26-1-2018
// //
module ram ( module ram (
input clk, // clock signal input clk, // clock signal
input ena,
input [15:0] address, // address bus input [15:0] address, // address bus
input w_en, // active high write enable strobe input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input) input [7:0] din, // 8-bit data bus (input)
output reg [7:0] dout // 8-bit data bus (output) output reg [7:0] dout // 8-bit data bus (output)
); );
reg [7:0] ram_data[0:49151]; parameter SIZE = 49152;
reg [7:0] ram_data[0:SIZE-1];
//initial //initial
// $readmemh("roms/ram.hex", ram_data, 0, 8191); // $readmemh("roms/ram.hex", ram_data, 0, 8191);
always @(posedge clk) always @(posedge clk)
begin begin
dout <= ram_data[address]; dout <= ram_data[address];
if (w_en) ram_data[address] <= din; if (w_en) ram_data[address] <= din;
end end
endmodule endmodule