From 35876b4b7d68ef334295718a4d14209b8d04b94a Mon Sep 17 00:00:00 2001 From: nino-porcino Date: Sun, 2 Jan 2022 16:24:57 +0100 Subject: [PATCH] use multiple unison clocks --- rtl/apple1.v | 11 ++++++----- rtl/apple1_mist.sv | 29 +++++++++++++++-------------- rtl/clock.v | 38 +++++++++++++++++--------------------- rtl/pll.v | 16 ++++++++-------- rtl/ps2keyboard.v | 10 +++++----- 5 files changed, 51 insertions(+), 53 deletions(-) diff --git a/rtl/apple1.v b/rtl/apple1.v index 446843c..cdc268f 100644 --- a/rtl/apple1.v +++ b/rtl/apple1.v @@ -23,11 +23,12 @@ // module apple1( - input clk7, // 7 MHz master clock input reset, // reset + input sys_clock, // system clock + input pixel_clock, // 7 MHz pixel clock input cpu_clken, // cpu clock enable - + // RAM interface output [15:0] ram_addr, output [7:0] ram_din, @@ -65,7 +66,7 @@ assign ram_wr = we & ram_cs; // 6502 arlet_6502 arlet_6502( - .clk (clk7), + .clk (sys_clock), .enable (cpu_clken), .rst (reset), .ab (addr), @@ -92,7 +93,7 @@ assign ram_wr = we & ram_cs; // PS/2 keyboard interface wire [7:0] ps2_dout; ps2keyboard keyboard( - .clk7(clk7), + .clk(sys_clock), .rst(reset), .key_clk(ps2_clk), .key_din(ps2_din), @@ -102,7 +103,7 @@ assign ram_wr = we & ram_cs; ); display display( - .clk(clk7), + .clk(pixel_clock), .enable(display_cs & cpu_clken), .rst(reset), diff --git a/rtl/apple1_mist.sv b/rtl/apple1_mist.sv index 62ac0e2..aa86565 100644 --- a/rtl/apple1_mist.sv +++ b/rtl/apple1_mist.sv @@ -90,8 +90,6 @@ localparam conf_str_len = $size(CONF_STR)>>3; wire st_reset_switch = buttons[1]; wire st_menu_reset = status[6]; -wire clk7; // the 14.31818 MHz clock -wire clk_osd; // x2 clock for the OSD menu wire r, g, b; wire hs, vs; @@ -116,6 +114,8 @@ wire reset_button = status[0] | st_menu_reset | st_reset_switch | !pll_locked; wire pll_locked; +wire pixel_clock; // the 14.31818 MHz clock +wire clk_osd; // x2 clock for the OSD menu wire sdram_clock; // cpu x 7 x 8 for sdram.v interface wire sdram_clock_ph; // cpu x 7 x 8 phase shifted -2.5 ns @@ -123,8 +123,8 @@ pll pll ( .inclk0(CLOCK_27), .locked(pll_locked), - .c0(clk_osd), // x2 clock for OSD menu - .c1(clk7), // 7.15909 MHz (14.318180/2) + .c0( clk_osd ), // x2 video clock for OSD menu + .c1( pixel_clock ), // 7.15909 MHz (14.318180/2) .c2( sdram_clock ), // cpu x 7 x 8 .c3( sdram_clock_ph ) // cpu x 7 x 8 phase shifted -2.5 ns ); @@ -164,7 +164,7 @@ downloader .ROM_done ( ROM_loaded ), // external ram interface - .clk ( clk7 ), + .clk ( sdram_clock ), .clk_ena ( cpu_clken ), .wr ( download_wr ), .addr ( download_addr ), @@ -179,7 +179,7 @@ downloader // RAM ram ram( - .clk (clk7 ), + .clk (sdram_clock), .ena (cpu_clken ), .address(sdram_addr[15:0]), .w_en (sdram_wr ), @@ -225,7 +225,7 @@ assign LED = ~dummy; // WozMon ROM wire [7:0] rom_dout; rom_wozmon rom_wozmon( - .clk(clk7), + .clk(sdram_clock), .address(cpu_addr[7:0]), .dout(rom_dout) ); @@ -233,7 +233,7 @@ rom_wozmon rom_wozmon( // Basic ROM wire [7:0] basic_dout; rom_basic rom_basic( - .clk(clk7), + .clk(sdram_clock), .address(cpu_addr[11:0]), .dout(basic_dout) ); @@ -254,11 +254,12 @@ wire [7:0] bus_dout = basic_cs ? basic_dout : 8'b0; apple1 apple1 -( - .clk7(clk7), - .reset(reset_button), +( + .reset(reset_button), - .cpu_clken(cpu_clken), // apple1 outputs the CPU clock enable + .sys_clock(sdram_clock), // system clock + .pixel_clock(pixel_clock), // pixel clock 7 Mhz + .cpu_clken(cpu_clken), // CPU clock enable // RAM interface .ram_addr (cpu_addr), @@ -326,7 +327,7 @@ user_io user_io ( .conf_str (CONF_STR ), - .clk_sys (clk7 ), + .clk_sys (sdram_clock ), .SPI_CLK (SPI_SCK ), .SPI_SS_IO (CONF_DATA0 ), @@ -418,7 +419,7 @@ wire cpu_clken; // provides the cpu clock enable signal derived from main clock //wire cpu_clken; clock clock( - .clk7 ( clk7 ), // input: main clock + .sys_clock( sdram_clock ), // input: main clock .reset ( reset_button ), // input: reset signal .cpu_clken( cpu_clken ) // output: cpu clock enable ); diff --git a/rtl/clock.v b/rtl/clock.v index 0178976..42127dd 100644 --- a/rtl/clock.v +++ b/rtl/clock.v @@ -25,31 +25,27 @@ module clock ( - input clk7, // 7MHz clock master clock - input reset, // reset + input sys_clock, // master clock + input reset, // reset - // Clock enables - output reg cpu_clken // 1MHz clock enable for the CPU and devices + // Clock enables + output reg cpu_clken // 1MHz clock enable for the CPU and devices ); - // generate clock enable once every - // 14 clocks. This will (hopefully) make - // the 6502 run at 1 MHz - // - // the clock division counter is synchronously - // reset using rst_n to avoid undefined signals - // in simulation - // - - reg [4:0] clk_div; - always @(posedge clk7) - begin - if (clk_div == 7 || reset ) - clk_div <= 0; + reg [7:0] clk_div; + always @(posedge sys_clock or posedge reset) + begin + if(reset) begin + clk_div <= 0; + end + else begin + if (clk_div == 6) + clk_div <= 0; else - clk_div <= clk_div + 1'b1; + clk_div <= clk_div + 1; - cpu_clken <= (clk_div[4:0] == 0); - end + cpu_clken <= (clk_div[7:0] == 0); + end + end endmodule diff --git a/rtl/pll.v b/rtl/pll.v index 77902f4..448bfdd 100644 --- a/rtl/pll.v +++ b/rtl/pll.v @@ -123,11 +123,11 @@ module pll ( altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 715909, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 337500, + altpll_component.clk2_divide_by = 2700000, altpll_component.clk2_duty_cycle = 50, altpll_component.clk2_multiply_by = 715909, altpll_component.clk2_phase_shift = "0", - altpll_component.clk3_divide_by = 337500, + altpll_component.clk3_divide_by = 2700000, altpll_component.clk3_duty_cycle = 50, altpll_component.clk3_multiply_by = 715909, altpll_component.clk3_phase_shift = "-2500", @@ -214,8 +214,8 @@ endmodule // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318180" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.159090" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.272720" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "57.272720" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "7.159090" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "7.159090" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -251,8 +251,8 @@ endmodule // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.31818000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.15909000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.27272000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "57.27272000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "7.15909000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "7.15909000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" @@ -320,11 +320,11 @@ endmodule // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "715909" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "337500" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2700000" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "715909" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "337500" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2700000" // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "715909" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2500" diff --git a/rtl/ps2keyboard.v b/rtl/ps2keyboard.v index 20a4873..2259327 100644 --- a/rtl/ps2keyboard.v +++ b/rtl/ps2keyboard.v @@ -22,7 +22,7 @@ // module ps2keyboard ( - input clk7, // 25MHz clock + input clk, // 25MHz clock input rst, // active high reset // I/O interface to keyboard @@ -43,7 +43,7 @@ module ps2keyboard ( reg [7:0] rx; // scancode receive buffer // wire ps2_clkdb; // debounced PS/2 clock signal - reg prev_ps2_clkdb; // previous clock state (in clk7 domain) + reg prev_ps2_clkdb; // previous clock state (in clk domain) // keyboard translation signals reg [7:0] ascii; // ASCII code of received character @@ -54,13 +54,13 @@ module ps2keyboard ( // debounce ps2clk_debounce // ( - // .clk7(clk7), + // .clk(clk), // .rst(rst), // .sig_in(key_clk), // .sig_out(ps2_clkdb) // ); - always @(posedge clk7 or posedge rst) + always @(posedge clk or posedge rst) begin if (rst) begin @@ -112,7 +112,7 @@ module ps2keyboard ( localparam S_KEYE0 = 3'b010; // extended key state localparam S_KEYE0F0 = 3'b011; // extended release state - always @(posedge clk7 or posedge rst) + always @(posedge clk or posedge rst) begin if (rst) begin