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https://github.com/nippur72/Apple1_MiST.git
synced 2024-06-16 15:29:32 +00:00
prepare for refresh rate emulation
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parent
c3e75e4859
commit
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@ -552,7 +552,7 @@ clock clock(
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.reset ( reset_button ), // input: reset signal
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.reset ( reset_button ), // input: reset signal
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.cpu_clock ( cpu_clock ),
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.cpu_clock ( cpu_clock ),
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.cpu_clken ( cpu_clken ), // output: cpu clock enable
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.cpu_clken ( cpu_clken ), // output: cpu clock enable (phi2)
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.pixel_clken( pixel_clken ) // output: pixel clock enable
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.pixel_clken( pixel_clken ) // output: pixel clock enable
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);
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);
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16
rtl/clock.v
16
rtl/clock.v
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@ -12,28 +12,34 @@ module clock
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localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz
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localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz
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localparam PIXEL_DIVISOR = 8; // (sys_clock / PIXEL_DIVISOR) = 7 MHz
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localparam PIXEL_DIVISOR = 8; // (sys_clock / PIXEL_DIVISOR) = 7 MHz
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localparam REFRESH_DIVISOR = 65; //
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reg [5:0] counter_cpu;
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reg [5:0] counter_cpu;
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reg [2:0] counter_pixel;
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reg [2:0] counter_pixel;
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reg [7:0] counter_refresh;
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always @(posedge sys_clock or posedge reset)
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always @(posedge sys_clock or posedge reset)
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begin
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begin
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if(reset) begin
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if(reset) begin
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counter_cpu <= 0;
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counter_cpu <= 0;
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counter_pixel <= 0;
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counter_pixel <= 0;
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counter_refresh <= 0;
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end
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end
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else begin
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else begin
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if (counter_cpu == (CPU_DIVISOR-1)) counter_cpu <= 0;
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if (counter_cpu == (CPU_DIVISOR-1)) begin
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else counter_cpu <= counter_cpu + 1;
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counter_cpu <= 0;
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counter_refresh <= (counter_refresh == REFRESH_DIVISOR-1) ? 0 : counter_refresh + 1;
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end
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else
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counter_cpu <= counter_cpu + 1;
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if (counter_pixel == (PIXEL_DIVISOR-1)) counter_pixel <= 0;
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counter_pixel <= (counter_pixel == PIXEL_DIVISOR-1) ? 0 : counter_pixel + 1;
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else counter_pixel <= counter_pixel + 1;
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end
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end
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end
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end
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assign cpu_clken = counter_cpu == 0;
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assign cpu_clken = counter_cpu == 0 /*&& counter_refresh > 3*/;
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assign pixel_clken = counter_pixel == 0;
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assign pixel_clken = counter_pixel == 0;
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assign cpu_clock = counter_pixel < 4 ? 1 : 0;
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assign cpu_clock = counter_pixel < 4 ? 1 : 0;
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