mirror of
https://github.com/nippur72/Apple1_MiST.git
synced 2024-06-09 15:29:30 +00:00
use sdram clock as sys_clock
This commit is contained in:
parent
7f5f294496
commit
b7a1632485
|
@ -27,6 +27,7 @@ module apple1(
|
||||||
|
|
||||||
input sys_clock, // system clock
|
input sys_clock, // system clock
|
||||||
input pixel_clock, // 7 MHz pixel clock
|
input pixel_clock, // 7 MHz pixel clock
|
||||||
|
input pixel_clken, // 7 MHz pixel clock
|
||||||
input cpu_clken, // cpu clock enable
|
input cpu_clken, // cpu clock enable
|
||||||
|
|
||||||
// RAM interface
|
// RAM interface
|
||||||
|
@ -105,8 +106,8 @@ assign ram_wr = we & ram_cs;
|
||||||
display display(
|
display display(
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
|
|
||||||
.pixel_clock(pixel_clock),
|
.pixel_clock(sys_clock),
|
||||||
.pixel_clken(1),
|
.pixel_clken(pixel_clken),
|
||||||
.cpu_clken(cpu_clken & display_cs),
|
.cpu_clken(cpu_clken & display_cs),
|
||||||
|
|
||||||
.vga_h_sync(vga_h_sync),
|
.vga_h_sync(vga_h_sync),
|
||||||
|
|
|
@ -261,6 +261,7 @@ apple1 apple1
|
||||||
.sys_clock(sdram_clock), // system clock
|
.sys_clock(sdram_clock), // system clock
|
||||||
.pixel_clock(pixel_clock), // pixel clock 7 Mhz
|
.pixel_clock(pixel_clock), // pixel clock 7 Mhz
|
||||||
.cpu_clken(cpu_clken), // CPU clock enable
|
.cpu_clken(cpu_clken), // CPU clock enable
|
||||||
|
.pixel_clken(pixel_clken), // pixel clock enable
|
||||||
|
|
||||||
// RAM interface
|
// RAM interface
|
||||||
.ram_addr (cpu_addr),
|
.ram_addr (cpu_addr),
|
||||||
|
@ -416,12 +417,15 @@ sdram sdram (
|
||||||
/******************************************************************************************/
|
/******************************************************************************************/
|
||||||
/******************************************************************************************/
|
/******************************************************************************************/
|
||||||
|
|
||||||
wire cpu_clken; // provides the cpu clock enable signal derived from main clock
|
wire cpu_clken; // provides the cpu clock enable signal derived from main clock
|
||||||
|
wire pixel_clken; // provides the cpu clock enable signal derived from main clock
|
||||||
|
|
||||||
clock clock(
|
clock clock(
|
||||||
.sys_clock( sdram_clock ), // input: main clock
|
.sys_clock ( sdram_clock ), // input: main clock
|
||||||
.reset ( reset_button ), // input: reset signal
|
.reset ( reset_button ), // input: reset signal
|
||||||
.cpu_clken( cpu_clken ) // output: cpu clock enable
|
|
||||||
|
.cpu_clken ( cpu_clken ), // output: cpu clock enable
|
||||||
|
.pixel_clken( pixel_clken ) // output: pixel clock enable
|
||||||
);
|
);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
55
rtl/clock.v
55
rtl/clock.v
|
@ -1,50 +1,35 @@
|
||||||
// Licensed to the Apache Software Foundation (ASF) under one
|
|
||||||
// or more contributor license agreements. See the NOTICE file
|
|
||||||
// distributed with this work for additional information
|
|
||||||
// regarding copyright ownership. The ASF licenses this file
|
|
||||||
// to you under the Apache License, Version 2.0 (the
|
|
||||||
// "License"); you may not use this file except in compliance
|
|
||||||
// with the License. You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing,
|
|
||||||
// software distributed under the License is distributed on an
|
|
||||||
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
|
|
||||||
// KIND, either express or implied. See the License for the
|
|
||||||
// specific language governing permissions and limitations
|
|
||||||
// under the License.
|
|
||||||
//
|
|
||||||
// Description: Clock divider to provide clock enables for
|
|
||||||
// devices.
|
|
||||||
//
|
|
||||||
// Author.....: Alan Garfield
|
|
||||||
// Niels A. Moseley
|
|
||||||
// Date.......: 29-1-2018
|
|
||||||
//
|
|
||||||
|
|
||||||
module clock
|
module clock
|
||||||
(
|
(
|
||||||
input sys_clock, // master clock
|
input sys_clock, // master clock at cpu x 7 x 8
|
||||||
input reset, // reset
|
input reset, // reset
|
||||||
|
|
||||||
// Clock enables
|
output reg cpu_clken, // 1MHz clock enable for the CPU
|
||||||
output reg cpu_clken // 1MHz clock enable for the CPU and devices
|
output reg pixel_clken // 7MHz clock enable for the display
|
||||||
);
|
);
|
||||||
|
|
||||||
reg [7:0] clk_div;
|
localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz
|
||||||
|
localparam PIXEL_DIVISOR = 8; // (sys_clock / PIXEL_DIVISOR) = 7 MHz
|
||||||
|
|
||||||
|
reg [5:0] counter_cpu;
|
||||||
|
reg [2:0] counter_pixel;
|
||||||
|
|
||||||
always @(posedge sys_clock or posedge reset)
|
always @(posedge sys_clock or posedge reset)
|
||||||
begin
|
begin
|
||||||
if(reset) begin
|
if(reset) begin
|
||||||
clk_div <= 0;
|
counter_cpu <= 0;
|
||||||
|
counter_pixel <= 0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if (clk_div == 6)
|
|
||||||
clk_div <= 0;
|
if (counter_cpu == (CPU_DIVISOR-1)) counter_cpu <= 0;
|
||||||
else
|
else counter_cpu <= counter_cpu + 1;
|
||||||
clk_div <= clk_div + 1;
|
|
||||||
|
|
||||||
cpu_clken <= (clk_div[7:0] == 0);
|
if (counter_pixel == (PIXEL_DIVISOR-1)) counter_pixel <= 0;
|
||||||
|
else counter_pixel <= counter_pixel + 1;
|
||||||
|
|
||||||
|
cpu_clken <= counter_cpu == 0;
|
||||||
|
pixel_clken <= counter_pixel == 0;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
16
rtl/pll.v
16
rtl/pll.v
|
@ -123,11 +123,11 @@ module pll (
|
||||||
altpll_component.clk1_duty_cycle = 50,
|
altpll_component.clk1_duty_cycle = 50,
|
||||||
altpll_component.clk1_multiply_by = 715909,
|
altpll_component.clk1_multiply_by = 715909,
|
||||||
altpll_component.clk1_phase_shift = "0",
|
altpll_component.clk1_phase_shift = "0",
|
||||||
altpll_component.clk2_divide_by = 2700000,
|
altpll_component.clk2_divide_by = 337500,
|
||||||
altpll_component.clk2_duty_cycle = 50,
|
altpll_component.clk2_duty_cycle = 50,
|
||||||
altpll_component.clk2_multiply_by = 715909,
|
altpll_component.clk2_multiply_by = 715909,
|
||||||
altpll_component.clk2_phase_shift = "0",
|
altpll_component.clk2_phase_shift = "0",
|
||||||
altpll_component.clk3_divide_by = 2700000,
|
altpll_component.clk3_divide_by = 337500,
|
||||||
altpll_component.clk3_duty_cycle = 50,
|
altpll_component.clk3_duty_cycle = 50,
|
||||||
altpll_component.clk3_multiply_by = 715909,
|
altpll_component.clk3_multiply_by = 715909,
|
||||||
altpll_component.clk3_phase_shift = "-2500",
|
altpll_component.clk3_phase_shift = "-2500",
|
||||||
|
@ -214,8 +214,8 @@ endmodule
|
||||||
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318180"
|
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318180"
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.159090"
|
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.159090"
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "7.159090"
|
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.272720"
|
||||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "7.159090"
|
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "57.272720"
|
||||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||||
|
@ -251,8 +251,8 @@ endmodule
|
||||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.31818000"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.31818000"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.15909000"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.15909000"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "7.15909000"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.27272000"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "7.15909000"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "57.27272000"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||||
|
@ -320,11 +320,11 @@ endmodule
|
||||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "715909"
|
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "715909"
|
||||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2700000"
|
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "337500"
|
||||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "715909"
|
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "715909"
|
||||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||||
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2700000"
|
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "337500"
|
||||||
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||||
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "715909"
|
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "715909"
|
||||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2500"
|
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2500"
|
||||||
|
|
Loading…
Reference in New Issue
Block a user