# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.1.0 Build 162 10/23/2013 SJ Web Edition # Date created = 11:23:36 April 10, 2018 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # apple-one_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:11:27 JANUARY 26, 2018" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files # Classic Timing Assignments # ========================== set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name TOP_LEVEL_ENTITY apple1_mist set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 # Fitter Assignments # ================== set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF set_global_assignment -name ENABLE_NCE_PIN OFF set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" # Assembler Assignments # ===================== set_global_assignment -name USE_CONFIGURATION_DEVICE OFF set_global_assignment -name GENERATE_RBF_FILE ON # Power Estimation Assignments # ============================ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" # Advanced I/O Timing Assignments # =============================== set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall # start EDA_TOOL_SETTINGS(eda_simulation) # --------------------------------------- # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation # end EDA_TOOL_SETTINGS(eda_simulation) # ------------------------------------- # start DESIGN_PARTITION(Top) # --------------------------- # Incremental Compilation Assignments # =================================== set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # Pin & Location Assignments # ========================== set_location_assignment PIN_7 -to LED set_location_assignment PIN_54 -to CLOCK_27 set_location_assignment PIN_144 -to VGA_R[5] set_location_assignment PIN_143 -to VGA_R[4] set_location_assignment PIN_142 -to VGA_R[3] set_location_assignment PIN_141 -to VGA_R[2] set_location_assignment PIN_137 -to VGA_R[1] set_location_assignment PIN_135 -to VGA_R[0] set_location_assignment PIN_133 -to VGA_B[5] set_location_assignment PIN_132 -to VGA_B[4] set_location_assignment PIN_125 -to VGA_B[3] set_location_assignment PIN_121 -to VGA_B[2] set_location_assignment PIN_120 -to VGA_B[1] set_location_assignment PIN_115 -to VGA_B[0] set_location_assignment PIN_114 -to VGA_G[5] set_location_assignment PIN_113 -to VGA_G[4] set_location_assignment PIN_112 -to VGA_G[3] set_location_assignment PIN_111 -to VGA_G[2] set_location_assignment PIN_110 -to VGA_G[1] set_location_assignment PIN_106 -to VGA_G[0] set_location_assignment PIN_136 -to VGA_VS set_location_assignment PIN_119 -to VGA_HS set_location_assignment PIN_65 -to AUDIO_L set_location_assignment PIN_80 -to AUDIO_R set_location_assignment PIN_105 -to SPI_DO set_location_assignment PIN_88 -to SPI_DI set_location_assignment PIN_126 -to SPI_SCK set_location_assignment PIN_127 -to SPI_SS2 set_location_assignment PIN_91 -to SPI_SS3 set_location_assignment PIN_13 -to CONF_DATA0 set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" # end ENTITY(apple1_mist) # ----------------------- set_global_assignment -name VERILOG_FILE "rtl/mist-modules/user_io.v" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/sd_card.v" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/scandoubler.v" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/rgb2ypbpr.v" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/osd.v" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/mist_video.v" set_global_assignment -name QIP_FILE "rtl/mist-modules/mist_core.qip" set_global_assignment -name VHDL_FILE "rtl/mist-modules/mist.vhd" set_global_assignment -name QIP_FILE "rtl/mist-modules/mist.qip" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/data_io.v" set_global_assignment -name VHDL_FILE "rtl/mist-modules/dac.vhd" set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mist-modules/cofi.sv" set_global_assignment -name VERILOG_FILE "rtl/mist-modules/arcade_inputs.v" set_global_assignment -name VERILOG_FILE rtl/arlet_6502/cpu.v set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v set_global_assignment -name VERILOG_FILE rtl/apple1.v set_global_assignment -name VERILOG_FILE rtl/clock.v set_global_assignment -name VERILOG_FILE rtl/pwr_reset.v set_global_assignment -name VERILOG_FILE rtl/ram.v set_global_assignment -name VERILOG_FILE rtl/rom_basic.v set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v set_global_assignment -name VERILOG_FILE rtl/vram.v set_global_assignment -name VERILOG_FILE rtl/uart.v set_global_assignment -name VERILOG_FILE rtl/ps2keyboard.v set_global_assignment -name VERILOG_FILE rtl/vga.v set_global_assignment -name VERILOG_FILE rtl/async_tx_rx.v set_global_assignment -name VERILOG_FILE rtl/font_rom.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv set_global_assignment -name VERILOG_FILE rtl/scandoubler.v set_global_assignment -name QIP_FILE rtl/pll.qip set_global_assignment -name VERILOG_FILE rtl/osd.v set_global_assignment -name VERILOG_FILE rtl/mist_io.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/apple1_mist.sv set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top