264 lines
7.5 KiB
Verilog
264 lines
7.5 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple1 hardware core
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module apple1(
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input clk14, // 25 MHz master clock
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input rst_n, // active low synchronous reset (needed for simulation)
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts, // clear to send flag to computer
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// I/O interface to keyboard
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input ps2_clk, // PS/2 keyboard serial clock input
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input ps2_din, // PS/2 keyboard serial data input
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input ps2_select, // Input to select the PS/2 keyboard instead of the UART
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output vga_red, // red VGA signal
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output vga_grn, // green VGA signal
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output vga_blu, // blue VGA signal
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input vga_cls, // clear screen button
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// Debugging ports
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output [15:0] pc_monitor // spy for program counter / debugging
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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wire [15:0] ab;
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wire [7:0] dbi;
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wire [7:0] dbo;
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wire we;
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//////////////////////////////////////////////////////////////////////////
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// Clocks
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wire cpu_clken;
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clock clock(
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.clk14(clk14),
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.rst_n(rst_n),
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.cpu_clken(cpu_clken)
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);
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//////////////////////////////////////////////////////////////////////////
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// Reset
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wire rst;
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pwr_reset pwr_reset(
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.clk14(clk14),
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.rst_n(rst_n),
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.enable(cpu_clken),
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.rst(rst)
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);
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//////////////////////////////////////////////////////////////////////////
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// 6502
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arlet_6502 arlet_6502(
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.clk (clk14),
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.enable (cpu_clken),
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.rst (rst),
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.ab (ab),
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.dbi (dbi),
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.dbo (dbo),
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.we (we),
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.irq_n (1'b1),
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.nmi_n (1'b1),
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.ready (cpu_clken),
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.pc_monitor (pc_monitor)
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);
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//////////////////////////////////////////////////////////////////////////
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// Address Decoding
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wire ram_cs = (ab[15:13] == 3'b000); // 0x0000 -> 0x1FFF
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// font mode, background and foreground colour
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wire vga_mode_cs = (ab[15:2] == 14'b11000000000000); // 0xC000 -> 0xC003
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// RX: Either keyboard or UART input
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// TX: Always VGA and UART output
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wire rx_cs = (ab[15:1] == 15'b110100000001000); // 0xD010 -> 0xD011
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wire tx_cs = (ab[15:1] == 15'b110100000001001); // 0xD012 -> 0xD013
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// select UART on transmit but only receive when PS/2 is not selected.
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wire uart_cs = tx_cs | ((~ps2_select) & rx_cs);
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// select PS/2 keyboard input when selected.
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wire ps2kb_cs = ps2_select & rx_cs;
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// VGA always get characters when they are sent.
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wire vga_cs = tx_cs;
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wire basic_cs = (ab[15:12] == 4'b1110); // 0xE000 -> 0xEFFF
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wire rom_cs = (ab[15:8] == 8'b11111111); // 0xFF00 -> 0xFFFF
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//////////////////////////////////////////////////////////////////////////
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// RAM and ROM
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// RAM
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wire [7:0] ram_dout;
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ram ram(
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.clk(clk14),
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.address(ab[12:0]),
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.w_en(we & ram_cs),
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.din(dbo),
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.dout(ram_dout)
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);
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// WozMon ROM
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wire [7:0] rom_dout;
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rom_wozmon rom_wozmon(
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.clk(clk14),
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.address(ab[7:0]),
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.dout(rom_dout)
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);
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// Basic ROM
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wire [7:0] basic_dout;
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rom_basic rom_basic(
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.clk(clk14),
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.address(ab[11:0]),
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.dout(basic_dout)
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);
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//////////////////////////////////////////////////////////////////////////
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// Peripherals
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// UART
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wire [7:0] uart_dout;
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uart #(
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`ifdef SIM
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100, 10, 2 // for simulation don't need real baud rates
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`else
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25000000, 115200, 8 // 25MHz, 115200 baud, 8 times RX oversampling
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`endif
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) my_uart(
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.clk(clk14),
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.enable(uart_cs & cpu_clken),
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.rst(rst),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.address(ab[1:0]), // for uart
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.w_en(we & uart_cs),
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.din(dbo),
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.dout(uart_dout)
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);
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// PS/2 keyboard interface
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wire [7:0] ps2_dout;
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ps2keyboard keyboard(
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.clk14(clk14),
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.rst(rst),
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.key_clk(ps2_clk),
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.key_din(ps2_din),
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.cs(ps2kb_cs),
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.address(ab[0]),
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.dout(ps2_dout)
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);
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// VGA Display interface
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reg [2:0] fg_colour;
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reg [2:0] bg_colour;
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reg [1:0] font_mode;
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reg [7:0] vga_mode_dout;
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vga vga(
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.clk14(clk14),
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.enable(vga_cs & cpu_clken),
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.rst(rst),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.address(ab[0]),
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.w_en(we & vga_cs),
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.din(dbo),
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.mode(font_mode),
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.fg_colour(fg_colour),
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.bg_colour(bg_colour),
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.clr_screen(vga_cls)
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);
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// Handle font mode and foreground and background
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// colours. This so isn't Apple One authentic, but
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// it can't hurt to have some fun. :D
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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begin
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font_mode <= 2'b0;
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fg_colour <= 3'd7;
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bg_colour <= 3'd0;
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end
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else
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begin
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case (ab[1:0])
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2'b00:
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begin
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vga_mode_dout = {6'b0, font_mode};
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if (vga_mode_cs & we & cpu_clken)
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font_mode <= dbo[1:0];
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end
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2'b01:
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begin
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vga_mode_dout = {5'b0, fg_colour};
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if (vga_mode_cs & we & cpu_clken)
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fg_colour <= dbo[2:0];
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end
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2'b10:
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begin
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vga_mode_dout = {5'b0, bg_colour};
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if (vga_mode_cs & we & cpu_clken)
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bg_colour <= dbo[2:0];
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end
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default:
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vga_mode_dout = 8'b0;
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endcase
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end
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end
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//////////////////////////////////////////////////////////////////////////
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// CPU Data In MUX
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// link up chip selected device to cpu input
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assign dbi = ram_cs ? ram_dout :
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rom_cs ? rom_dout :
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basic_cs ? basic_dout :
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uart_cs ? uart_dout :
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ps2kb_cs ? ps2_dout :
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vga_mode_cs ? vga_mode_dout :
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8'hFF;
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endmodule
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