109 lines
2.2 KiB
Verilog
109 lines
2.2 KiB
Verilog
/*
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* ALU.
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*
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* AI and BI are 8 bit inputs. Result in OUT.
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* CI is Carry In.
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* CO is Carry Out.
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*
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* op[3:0] is defined as follows:
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*
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* 0011 AI + BI
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* 0111 AI - BI
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* 1011 AI + AI
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* 1100 AI | BI
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* 1101 AI & BI
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* 1110 AI ^ BI
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* 1111 AI
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*
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*/
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module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
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input clk;
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input right;
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input [3:0] op; // operation
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input [7:0] AI;
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input [7:0] BI;
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input CI;
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input BCD; // BCD style carry
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output [7:0] OUT;
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output CO;
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output V;
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output Z;
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output N;
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output HC;
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input RDY;
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reg [7:0] OUT;
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reg CO;
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wire V;
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wire Z;
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reg N;
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reg HC;
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reg AI7;
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reg BI7;
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reg [8:0] temp_logic;
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reg [7:0] temp_BI;
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reg [4:0] temp_l;
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reg [4:0] temp_h;
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wire [8:0] temp = { temp_h, temp_l[3:0] };
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wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
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// calculate the logic operations. The 'case' can be done in 1 LUT per
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// bit. The 'right' shift is a simple mux that can be implemented by
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// F5MUX.
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always @* begin
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case( op[1:0] )
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2'b00: temp_logic = AI | BI;
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2'b01: temp_logic = AI & BI;
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2'b10: temp_logic = AI ^ BI;
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2'b11: temp_logic = AI;
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endcase
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if( right )
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temp_logic = { AI[0], CI, AI[7:1] };
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end
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// Add logic result to BI input. This only makes sense when logic = AI.
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// This stage can be done in 1 LUT per bit, using carry chain logic.
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always @* begin
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case( op[3:2] )
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2'b00: temp_BI = BI; // A+B
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2'b01: temp_BI = ~BI; // A-B
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2'b10: temp_BI = temp_logic; // A+A
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2'b11: temp_BI = 0; // A+0
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endcase
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end
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// HC9 is the half carry bit when doing BCD add
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wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
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// CO9 is the carry-out bit when doing BCD add
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wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
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// combined half carry bit
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wire temp_HC = temp_l[4] | HC9;
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// perform the addition as 2 separate nibble, so we get
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// access to the half carry flag
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always @* begin
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temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
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temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
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end
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// calculate the flags
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always @(posedge clk)
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if( RDY ) begin
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AI7 <= AI[7];
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BI7 <= temp_BI[7];
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OUT <= temp[7:0];
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CO <= temp[8] | CO9;
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N <= temp[7];
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HC <= temp_HC;
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end
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assign V = AI7 ^ BI7 ^ CO ^ N;
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assign Z = ~|OUT;
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endmodule
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