73 lines
2.2 KiB
Verilog
73 lines
2.2 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: A wrapper for Arlet Ottens 6502 CPU core
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module arlet_6502(
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input clk, // clock signal
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input enable, // clock enable strobe
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input rst, // active high reset signal
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output reg [15:0] ab, // address bus
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input [7:0] dbi, // 8-bit data bus (input)
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output reg [7:0] dbo, // 8-bit data bus (output)
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output reg we, // active high write enable strobe
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input irq_n, // active low interrupt request
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input nmi_n, // active low non-maskable interrupt
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input ready, // CPU updates when ready = 1
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output [15:0] pc_monitor // program counter monitor signal for debugging
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);
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wire [7:0] dbo_c;
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wire [15:0] ab_c;
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wire we_c;
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cpu arlet_cpu(
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.clk(clk),
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.reset(rst),
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.AB(ab_c),
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.DI(dbi),
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.DO(dbo_c),
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.WE(we_c),
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.IRQ(~irq_n),
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.NMI(~nmi_n),
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.RDY(ready),
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.PC_MONITOR(pc_monitor)
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);
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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ab <= 16'd0;
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dbo <= 8'd0;
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we <= 1'b0;
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end
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else
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if (enable)
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begin
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ab <= ab_c;
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dbo <= dbo_c;
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we <= we_c;
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end
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end
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endmodule
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