67 lines
1.7 KiB
Verilog
67 lines
1.7 KiB
Verilog
`include "../rtl/cpu/aholme/chip_6502_nodes.inc"
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module LOGIC (
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input [`NUM_NODES-1:0] i,
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output [`NUM_NODES-1:0] o);
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`include "chip_6502_logic.inc"
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endmodule
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module chip_6502 (
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input clk, // FPGA clock
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input phi, // 6502 clock
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input res,
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input so,
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input rdy,
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input nmi,
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input irq,
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input [7:0] dbi,
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output [7:0] dbo,
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output rw,
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output sync,
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output [15:0] ab);
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// Node states
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wire [`NUM_NODES-1:0] no;
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reg [`NUM_NODES-1:0] ni;
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reg [`NUM_NODES-1:0] q = 0;
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LOGIC logic_00 (.i(ni), .o(no));
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always @ (posedge clk)
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q <= no;
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always @* begin
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ni = q;
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ni[`NODE_vcc ] = 1'b1;
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ni[`NODE_vss ] = 1'b0;
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ni[`NODE_res ] = res;
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ni[`NODE_clk0] = phi;
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ni[`NODE_so ] = so;
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ni[`NODE_rdy ] = rdy;
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ni[`NODE_nmi ] = nmi;
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ni[`NODE_irq ] = irq;
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{ni[`NODE_db7],ni[`NODE_db6],ni[`NODE_db5],ni[`NODE_db4],
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ni[`NODE_db3],ni[`NODE_db2],ni[`NODE_db1],ni[`NODE_db0]} = dbi[7:0];
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end
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assign dbo[7:0] = {
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no[`NODE_db7],no[`NODE_db6],no[`NODE_db5],no[`NODE_db4],
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no[`NODE_db3],no[`NODE_db2],no[`NODE_db1],no[`NODE_db0]
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};
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assign ab[15:0] = {
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no[`NODE_ab15], no[`NODE_ab14], no[`NODE_ab13], no[`NODE_ab12],
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no[`NODE_ab11], no[`NODE_ab10], no[`NODE_ab9], no[`NODE_ab8],
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no[`NODE_ab7], no[`NODE_ab6], no[`NODE_ab5], no[`NODE_ab4],
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no[`NODE_ab3], no[`NODE_ab2], no[`NODE_ab1], no[`NODE_ab0]
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};
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assign rw = no[`NODE_rw];
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assign sync = no[`NODE_sync];
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endmodule
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