228 lines
7.8 KiB
Verilog
228 lines
7.8 KiB
Verilog
////////////////////////////////////////////////////////
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// RS-232 RX and TX module
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// (c) fpga4fun.com & KNJN LLC - 2003 to 2016
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// The RS-232 settings are fixed
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// TX: 8-bit data, 2 stop, no-parity
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// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
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////////////////////////////////////////////////////////
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module async_transmitter(
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input clk,
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input rst,
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input TxD_start,
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input [7:0] TxD_data,
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output TxD,
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output TxD_busy
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);
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// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
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// TxD_data is latched so that it doesn't have to stay valid while it is being sent
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parameter ClkFrequency = 25000000; // 25MHz
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parameter Baud = 115200;
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////////////////////////////////
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wire BitTick;
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BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .rst(rst), .enable(TxD_busy), .tick(BitTick));
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reg [3:0] TxD_state;
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reg [7:0] TxD_shift;
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wire TxD_ready = (TxD_state==0);
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assign TxD_busy = ~TxD_ready;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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TxD_state <= 0;
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TxD_shift <= 0;
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end
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else
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begin
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if(TxD_ready & TxD_start)
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TxD_shift <= TxD_data;
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else
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if(TxD_state[3] & BitTick)
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TxD_shift <= (TxD_shift >> 1);
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case(TxD_state)
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4'b0000: if(TxD_start) TxD_state <= 4'b0100;
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4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
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4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
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4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
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4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
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4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
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4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
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4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
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4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
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4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
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4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
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4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
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default: if(BitTick) TxD_state <= 4'b0000;
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endcase
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end
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end
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assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
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endmodule
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////////////////////////////////////////////////////////
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module async_receiver(
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input clk,
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input rst,
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input RxD,
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output reg RxD_data_ready,
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output reg [7:0] RxD_data, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
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// We also detect if a gap occurs in the received stream of characters
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// That can be useful if multiple characters are sent in burst
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// so that multiple characters can be treated as a "packet"
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output RxD_idle, // asserted when no data has been received for a while
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output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
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);
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parameter ClkFrequency = 25000000; // 12MHz
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parameter Baud = 115200;
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parameter Oversampling = 8; // needs to be a power of 2
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// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
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// 8 times oversampling by default, use 16 for higher quality reception
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////////////////////////////////
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reg [3:0] RxD_state;
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wire OversamplingTick;
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BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .rst(rst), .enable(1'b1), .tick(OversamplingTick));
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// synchronize RxD to our clk domain
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reg [1:0] RxD_sync; // 2'b11
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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RxD_sync <= 2'b11;
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else
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if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
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end
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// and filter it
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reg [1:0] Filter_cnt; // 2'b11
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reg RxD_bit; // 1'b1
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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Filter_cnt <= 2'b11;
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RxD_bit <= 1'b1;
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end
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else
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if(OversamplingTick)
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begin
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if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
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else if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
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if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
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else if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
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end
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end
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// and decide when is the good time to sample the RxD line
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function integer log2(input integer v);
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begin
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log2=0;
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while(v>>log2)
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log2 = log2 + 1;
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end
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endfunction
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localparam l2o = log2(Oversampling);
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reg [l2o-2:0] OversamplingCnt;
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always @(posedge clk)
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if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
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wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
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// now we can accumulate the RxD bits in a shift-register
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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RxD_state <= 0;
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else
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case(RxD_state)
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4'b0000: if(~RxD_bit) RxD_state <= 4'b0001; // start bit found?
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4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
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4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
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4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
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4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
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4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
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4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
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4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
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4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
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4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
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4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
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default: RxD_state <= 4'b0000;
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endcase
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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RxD_data <= 0;
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else
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if (sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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RxD_data_ready <= 0;
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else
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RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
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end
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reg [l2o+1:0] GapCnt;
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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GapCnt <= 0;
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else
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if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
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end
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assign RxD_idle = GapCnt[l2o+1];
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always @(posedge clk)
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RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
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endmodule
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////////////////////////////////////////////////////////
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module BaudTickGen(
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input clk, rst, enable,
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output tick // generate a tick at the specified baud rate * oversampling
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);
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parameter ClkFrequency = 25000000;
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parameter Baud = 115200;
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parameter Oversampling = 1;
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function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
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localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
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reg [AccWidth:0] Acc;
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localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
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localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
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always @(posedge clk)
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begin
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if (rst)
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Acc <= 0;
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else
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if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
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end
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assign tick = Acc[AccWidth];
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endmodule
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