56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Clock divider to provide clock enables for
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// devices.
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 29-1-2018
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//
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module clock
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(
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input clk14, // 14MHz clock master clock
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input rst_n, // active low synchronous reset
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// Clock enables
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output reg cpu_clken // 1MHz clock enable for the CPU and devices
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);
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// generate clock enable once every
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// 14 clocks. This will (hopefully) make
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// the 6502 run at 1 MHz
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//
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// the clock division counter is synchronously
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// reset using rst_n to avoid undefined signals
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// in simulation
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//
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reg [4:0] clk_div;
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always @(posedge clk14)
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begin
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if ((clk_div == 14) || (rst_n == 1'b0))
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clk_div <= 0;
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else
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clk_div <= clk_div + 1'b1;
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cpu_clken <= (clk_div[4:0] == 0);
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end
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endmodule
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