73 lines
2.0 KiB
Verilog
73 lines
2.0 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: PS/2 keyboard debounce logic to be used for the
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// clock line
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//
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// Author.....: Niels A. Moseley
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// Date.......: 8-2-2018
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//
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module debounce(
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input clk14, // 25MHz clock
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input rst, // active high reset
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input sig_in, // input signal
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output reg sig_out // debounced output signal
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);
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wire clk_enb; // enable triggering at clk14 divided by 64
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reg [5:0] clk_div; // clock divider counter
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reg sig_ff1; // first input signal synchronizer
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reg sig_ff2; // second input signal synchronizer
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assign clk_enb = (clk_div == 6'd0);
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// clock divider
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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clk_div <= 6'd0;
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else
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clk_div <= clk_div + 6'd1;
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end
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// debounce timer
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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begin
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sig_out <= 1'b0;
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sig_ff1 <= 1'b0;
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sig_ff2 <= 1'b0;
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end
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else if (clk_enb)
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begin
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// this runs ar approximately 391k Hz
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// giving a debounce time of around 2.5us
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sig_ff1 <= sig_in;
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sig_ff2 <= sig_ff1;
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if ((sig_ff1 ^ sig_ff2) == 1'd0)
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begin
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sig_out <= sig_ff2;
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end
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end
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end
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endmodule
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