168 lines
5.6 KiB
Verilog
168 lines
5.6 KiB
Verilog
module ledAndKey(
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input clk,
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input clk_en,
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input rst,
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input [3:0] display,
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input [7:0] digit1,
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input [7:0] digit2,
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input [7:0] digit3,
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input [7:0] digit4,
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input [7:0] digit5,
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input [7:0] digit6,
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input [7:0] digit7,
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input [7:0] digit8,
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input [7:0] leds,
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output reg [7:0] keys,
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output reg tm_cs,
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output tm_clk,
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inout tm_dio
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);
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localparam
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HIGH = 1'b1,
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LOW = 1'b0;
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localparam [7:0]
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C_READ = 8'b01000010,
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C_WRITE = 8'b01000000,
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C_DISP = 8'b10001111,
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C_ADDR = 8'b11000000;
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reg counter;
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reg [5:0] instruction_step;
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// set up tristate IO pin for display
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// tm_dio is physical pin
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// dio_in for reading from display
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// dio_out for sending to display
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// tm_rw selects input or output
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reg tm_rw;
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wire dio_in, dio_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) tm_dio_io (
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.PACKAGE_PIN(tm_dio),
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.OUTPUT_ENABLE(tm_rw),
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.D_IN_0(dio_in),
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.D_OUT_0(dio_out)
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);
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// setup tm1638 module with it's tristate IO
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// tm_in is read from module
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// tm_out is written to module
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// tm_latch triggers the module to read/write display
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// tm_rw selects read or write mode to display
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// busy indicates when module is busy
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// (another latch will interrupt)
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// tm_clk is the data clk
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// dio_in for reading from display
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// dio_out for sending to display
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//
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// tm_data the tristate io pin to module
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reg tm_latch;
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wire busy;
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wire [7:0] tm_data, tm_in;
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reg [7:0] tm_out;
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assign tm_in = tm_data;
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assign tm_data = tm_rw ? tm_out : 8'hZZ;
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tm1638 u_tm1638 (
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.clk(clk),
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.clk_en(clk_en),
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.rst(rst),
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.data_latch(tm_latch),
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.data(tm_data),
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.rw(tm_rw),
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.busy(busy),
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.sclk(tm_clk),
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.dio_in(dio_in),
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.dio_out(dio_out)
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);
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always @(posedge clk) begin
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if (clk_en) begin
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if (rst) begin
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instruction_step <= 6'b0;
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tm_cs <= HIGH;
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tm_rw <= HIGH;
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counter <= 1'b0;
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keys <= 8'b0;
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end else begin
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if (counter && ~busy) begin
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case (instruction_step)
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// *** KEYS ***
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1: {tm_cs, tm_rw} <= {LOW, HIGH};
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2: {tm_latch, tm_out} <= {HIGH, C_READ}; // read mode
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3: {tm_latch, tm_rw} <= {HIGH, LOW};
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// read back keys S1 - S8
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4: {keys[7], keys[3]} <= {tm_in[0], tm_in[4]};
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5: {tm_latch} <= {HIGH};
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6: {keys[6], keys[2]} <= {tm_in[0], tm_in[4]};
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7: {tm_latch} <= {HIGH};
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8: {keys[5], keys[1]} <= {tm_in[0], tm_in[4]};
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9: {tm_latch} <= {HIGH};
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10: {keys[4], keys[0]} <= {tm_in[0], tm_in[4]};
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11: {tm_cs} <= {HIGH};
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// *** DISPLAY ***
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12: {tm_cs, tm_rw} <= {LOW, HIGH};
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13: {tm_latch, tm_out} <= {HIGH, C_WRITE}; // write mode
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14: {tm_cs} <= {HIGH};
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15: {tm_cs, tm_rw} <= {LOW, HIGH};
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16: {tm_latch, tm_out} <= {HIGH, C_ADDR}; // set addr 0 pos
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17: {tm_latch, tm_out} <= {HIGH, digit1}; // Digit 1
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18: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[7]}}; // LED 1
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19: {tm_latch, tm_out} <= {HIGH, digit2}; // Digit 2
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20: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[6]}}; // LED 2
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21: {tm_latch, tm_out} <= {HIGH, digit3}; // Digit 3
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22: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[5]}}; // LED 3
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23: {tm_latch, tm_out} <= {HIGH, digit4}; // Digit 4
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24: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[4]}}; // LED 4
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25: {tm_latch, tm_out} <= {HIGH, digit5}; // Digit 5
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26: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[3]}}; // LED 5
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27: {tm_latch, tm_out} <= {HIGH, digit6}; // Digit 6
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28: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[2]}}; // LED 6
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29: {tm_latch, tm_out} <= {HIGH, digit7}; // Digit 7
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30: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[1]}}; // LED 7
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31: {tm_latch, tm_out} <= {HIGH, digit8}; // Digit 8
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32: {tm_latch, tm_out} <= {HIGH, {7'b0, leds[0]}}; // LED 8
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33: {tm_cs} <= {HIGH};
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34: {tm_cs, tm_rw} <= {LOW, HIGH};
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35: {tm_latch, tm_out} <= {HIGH, {4'b1000, display}}; // display
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36: {tm_cs, instruction_step} <= {HIGH, 6'b0};
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endcase
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instruction_step <= instruction_step + 1;
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end else if (busy) begin
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// pull latch low next clock cycle after module has been
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// latched
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tm_latch <= LOW;
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end
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counter <= ~counter;
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end
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end
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end
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endmodule
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