49 lines
1.2 KiB
VHDL
49 lines
1.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Delta-Sigma DAC
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--
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-- Refer to Xilinx Application Note XAPP154.
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--
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-- This DAC requires an external RC low-pass filter:
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--
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-- dac_o 0---XXXXX---+---0 analog audio
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-- 3k3 |
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-- === 4n7
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-- |
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-- GND
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dac is
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generic (
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C_bits : integer := 8
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);
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port (
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clk_i : in std_logic;
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res_n_i : in std_logic;
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dac_i : in std_logic_vector(C_bits-1 downto 0);
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dac_o : out std_logic
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);
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end dac;
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architecture rtl of dac is
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signal sig_in: unsigned(C_bits downto 0);
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begin
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seq: process(clk_i, res_n_i)
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begin
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if res_n_i = '0' then
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sig_in <= to_unsigned(2**C_bits, sig_in'length);
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dac_o <= '0';
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elsif rising_edge(clk_i) then
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-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
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--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
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sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
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dac_o <= sig_in(C_bits);
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end if;
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end process seq;
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end rtl;
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