260 lines
6.5 KiB
Verilog
260 lines
6.5 KiB
Verilog
//
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// data_io.v
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//
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// data_io for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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module data_io
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(
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input clk_sys,
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input SPI_SCK,
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input SPI_SS2,
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input SPI_SS4,
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input SPI_DI,
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inout SPI_DO,
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input clkref_n, // assert ioctl_wr one cycle after clkref stobe (negative active)
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// ARM -> FPGA download
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output reg ioctl_download = 0, // signal indicating an active download
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output reg ioctl_upload = 0, // signal indicating an active upload
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output reg [7:0] ioctl_index, // menu index used to upload the file ([7:6] - extension index, [5:0] - menu index)
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// Note: this is also set for user_io mounts.
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// Valid when ioctl_download = 1 or when img_mounted strobe is active in user_io.
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output reg ioctl_wr, // strobe indicating ioctl_dout valid
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output reg [24:0] ioctl_addr,
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output reg [7:0] ioctl_dout,
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input [7:0] ioctl_din,
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output reg [23:0] ioctl_fileext, // file extension
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output reg [31:0] ioctl_filesize // file size
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);
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parameter START_ADDR = 25'd0;
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parameter ROM_DIRECT_UPLOAD = 0;
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/////////////////////////////// DOWNLOADING ///////////////////////////////
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reg [7:0] data_w;
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reg [7:0] data_w2 = 0;
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reg [3:0] cnt;
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reg rclk = 0;
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reg rclk2 = 0;
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reg addr_reset = 0;
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reg downloading_reg = 0;
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reg uploading_reg = 0;
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reg reg_do;
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localparam DIO_FILE_TX = 8'h53;
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localparam DIO_FILE_TX_DAT = 8'h54;
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localparam DIO_FILE_INDEX = 8'h55;
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localparam DIO_FILE_INFO = 8'h56;
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localparam DIO_FILE_RX = 8'h57;
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localparam DIO_FILE_RX_DAT = 8'h58;
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assign SPI_DO = reg_do;
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// data_io has its own SPI interface to the io controller
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always@(negedge SPI_SCK or posedge SPI_SS2) begin : SPI_TRANSMITTER
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reg [7:0] dout_r;
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if(SPI_SS2) begin
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reg_do <= 1'bZ;
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end else begin
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if (cnt == 15) dout_r <= ioctl_din;
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reg_do <= dout_r[~cnt[2:0]];
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end
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end
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always@(posedge SPI_SCK, posedge SPI_SS2) begin : SPI_RECEIVER
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reg [6:0] sbuf;
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reg [24:0] addr;
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reg [7:0] cmd;
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reg [5:0] bytecnt;
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if(SPI_SS2) begin
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bytecnt <= 0;
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cnt <= 0;
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end else begin
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// don't shift in last bit. It is evaluated directly
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// when writing to ram
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if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
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// count 0-7 8-15 8-15 ...
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if(cnt != 15) cnt <= cnt + 1'd1;
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else cnt <= 8;
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// finished command byte
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if(cnt == 7) cmd <= {sbuf, SPI_DI};
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if(cnt == 15) begin
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case (cmd)
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// prepare/end transmission
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DIO_FILE_TX: begin
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// prepare
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if(SPI_DI) begin
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addr_reset <= ~addr_reset;
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downloading_reg <= 1;
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end else begin
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downloading_reg <= 0;
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end
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end
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DIO_FILE_RX: begin
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// prepare
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if(SPI_DI) begin
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addr_reset <= ~addr_reset;
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uploading_reg <= 1;
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end else begin
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uploading_reg <= 0;
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end
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end
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// command 0x57: DIO_FILE_RX_DAT
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// command 0x54: DIO_FILE_TX_DAT
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DIO_FILE_RX_DAT,
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DIO_FILE_TX_DAT: begin
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data_w <= {sbuf, SPI_DI};
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rclk <= ~rclk;
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end
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// expose file (menu) index
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DIO_FILE_INDEX: ioctl_index <= {sbuf, SPI_DI};
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// receiving FAT directory entry (mist-firmware/fat.h - DIRENTRY)
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DIO_FILE_INFO: begin
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bytecnt <= bytecnt + 1'd1;
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case (bytecnt)
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8'h08: ioctl_fileext[23:16] <= {sbuf, SPI_DI};
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8'h09: ioctl_fileext[15: 8] <= {sbuf, SPI_DI};
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8'h0A: ioctl_fileext[ 7: 0] <= {sbuf, SPI_DI};
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8'h1C: ioctl_filesize[ 7: 0] <= {sbuf, SPI_DI};
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8'h1D: ioctl_filesize[15: 8] <= {sbuf, SPI_DI};
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8'h1E: ioctl_filesize[23:16] <= {sbuf, SPI_DI};
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8'h1F: ioctl_filesize[31:24] <= {sbuf, SPI_DI};
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endcase
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end
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endcase
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end
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end
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end
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// direct SD Card->FPGA transfer
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generate if (ROM_DIRECT_UPLOAD == 1) begin
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always@(posedge SPI_SCK, posedge SPI_SS4) begin : SPI_DIRECT_RECEIVER
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reg [6:0] sbuf2;
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reg [2:0] cnt2;
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reg [9:0] bytecnt;
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if(SPI_SS4) begin
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cnt2 <= 0;
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bytecnt <= 0;
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end else begin
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// don't shift in last bit. It is evaluated directly
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// when writing to ram
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if(cnt2 != 7)
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sbuf2 <= { sbuf2[5:0], SPI_DO };
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cnt2 <= cnt2 + 1'd1;
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// received a byte
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if(cnt2 == 7) begin
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bytecnt <= bytecnt + 1'd1;
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// read 514 byte/sector (512 + 2 CRC)
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if (bytecnt == 513) bytecnt <= 0;
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// don't send the CRC bytes
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if (~bytecnt[9]) begin
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data_w2 <= {sbuf2, SPI_DO};
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rclk2 <= ~rclk2;
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end
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end
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end
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end
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end
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endgenerate
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always@(posedge clk_sys) begin : DATA_OUT
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// synchronisers
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reg rclkD, rclkD2;
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reg rclk2D, rclk2D2;
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reg addr_resetD, addr_resetD2;
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reg wr_int, wr_int_direct, rd_int;
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reg [24:0] addr;
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reg [31:0] filepos;
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// bring flags from spi clock domain into core clock domain
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{ rclkD, rclkD2 } <= { rclk, rclkD };
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{ rclk2D ,rclk2D2 } <= { rclk2, rclk2D };
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{ addr_resetD, addr_resetD2 } <= { addr_reset, addr_resetD };
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ioctl_wr <= 0;
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if (!downloading_reg) begin
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ioctl_download <= 0;
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wr_int <= 0;
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wr_int_direct <= 0;
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end
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if (!uploading_reg) begin
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ioctl_upload <= 0;
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rd_int <= 0;
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end
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if (~clkref_n) begin
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rd_int <= 0;
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wr_int <= 0;
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wr_int_direct <= 0;
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if (wr_int || wr_int_direct) begin
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ioctl_dout <= wr_int ? data_w : data_w2;
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ioctl_wr <= 1;
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addr <= addr + 1'd1;
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ioctl_addr <= addr;
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end
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if (rd_int) begin
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ioctl_addr <= ioctl_addr + 1'd1;
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end
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end
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// detect transfer start from the SPI receiver
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if(addr_resetD ^ addr_resetD2) begin
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addr <= START_ADDR;
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ioctl_addr <= START_ADDR;
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filepos <= 0;
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ioctl_download <= downloading_reg;
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ioctl_upload <= uploading_reg;
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end
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// detect new byte from the SPI receiver
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if (rclkD ^ rclkD2) begin
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wr_int <= downloading_reg;
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rd_int <= uploading_reg;
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end
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// direct transfer receiver
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if (rclk2D ^ rclk2D2 && filepos != ioctl_filesize) begin
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filepos <= filepos + 1'd1;
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wr_int_direct <= 1;
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end
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end
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endmodule
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