157 lines
3.7 KiB
Verilog
157 lines
3.7 KiB
Verilog
// A video pipeline for MiST. Just insert between the core video output and the VGA pins
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// Provides an optional scandoubler, a rotateable OSD and (optional) RGb->YPbPr conversion
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module mist_video
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(
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// master clock
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// it should be 4x (or 2x) pixel clock for the scandoubler
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input clk_sys,
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// OSD SPI interface
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input SPI_SCK,
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input SPI_SS3,
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input SPI_DI,
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// scanlines (00-none 01-25% 10-50% 11-75%)
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input [1:0] scanlines,
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// non-scandoubled pixel clock divider 0 - clk_sys/4, 1 - clk_sys/2
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input ce_divider,
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// 0 = HVSync 31KHz, 1 = CSync 15KHz
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input scandoubler_disable,
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// disable csync without scandoubler
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input no_csync,
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// YPbPr always uses composite sync
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input ypbpr,
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// Rotate OSD [0] - rotate [1] - left or right
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input [1:0] rotate,
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// composite-like blending
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input blend,
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// video in
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input [COLOR_DEPTH-1:0] R,
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input [COLOR_DEPTH-1:0] G,
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input [COLOR_DEPTH-1:0] B,
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input HSync,
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input VSync,
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// MiST video output signals
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output reg [5:0] VGA_R,
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output reg [5:0] VGA_G,
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output reg [5:0] VGA_B,
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output reg VGA_VS,
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output reg VGA_HS
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);
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parameter OSD_COLOR = 3'd4;
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parameter OSD_X_OFFSET = 10'd0;
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parameter OSD_Y_OFFSET = 10'd0;
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parameter SD_HCNT_WIDTH = 9;
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parameter COLOR_DEPTH = 6; // 1-6
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parameter OSD_AUTO_CE = 1'b1;
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parameter SYNC_AND = 1'b0; // 0 - XOR, 1 - AND
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wire [5:0] SD_R_O;
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wire [5:0] SD_G_O;
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wire [5:0] SD_B_O;
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wire SD_HS_O;
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wire SD_VS_O;
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wire pixel_ena;
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scandoubler #(SD_HCNT_WIDTH, COLOR_DEPTH) scandoubler
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(
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.clk_sys ( clk_sys ),
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.bypass ( scandoubler_disable ),
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.ce_divider ( ce_divider ),
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.scanlines ( scanlines ),
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.pixel_ena ( pixel_ena ),
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.hs_in ( HSync ),
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.vs_in ( VSync ),
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.r_in ( R ),
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.g_in ( G ),
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.b_in ( B ),
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.hs_out ( SD_HS_O ),
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.vs_out ( SD_VS_O ),
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.r_out ( SD_R_O ),
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.g_out ( SD_G_O ),
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.b_out ( SD_B_O )
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);
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wire [5:0] osd_r_o;
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wire [5:0] osd_g_o;
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wire [5:0] osd_b_o;
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osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR, OSD_AUTO_CE) osd
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(
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.clk_sys ( clk_sys ),
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.rotate ( rotate ),
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.ce ( pixel_ena ),
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.SPI_DI ( SPI_DI ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.R_in ( SD_R_O ),
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.G_in ( SD_G_O ),
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.B_in ( SD_B_O ),
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.HSync ( SD_HS_O ),
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.VSync ( SD_VS_O ),
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.R_out ( osd_r_o ),
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.G_out ( osd_g_o ),
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.B_out ( osd_b_o )
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);
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wire [5:0] cofi_r, cofi_g, cofi_b;
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wire cofi_hs, cofi_vs;
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cofi #(6) cofi (
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.clk ( clk_sys ),
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.pix_ce ( pixel_ena ),
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.enable ( blend ),
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.hblank ( ~SD_HS_O ),
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.hs ( SD_HS_O ),
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.vs ( SD_VS_O ),
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.red ( osd_r_o ),
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.green ( osd_g_o ),
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.blue ( osd_b_o ),
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.hs_out ( cofi_hs ),
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.vs_out ( cofi_vs ),
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.red_out ( cofi_r ),
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.green_out( cofi_g ),
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.blue_out( cofi_b )
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);
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wire hs, vs, cs;
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wire [5:0] r,g,b;
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RGBtoYPbPr #(6) rgb2ypbpr
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(
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.clk ( clk_sys ),
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.ena ( ypbpr ),
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.red_in ( cofi_r ),
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.green_in ( cofi_g ),
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.blue_in ( cofi_b ),
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.hs_in ( cofi_hs ),
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.vs_in ( cofi_vs ),
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.cs_in ( SYNC_AND ? (cofi_hs & cofi_vs) : ~(cofi_hs ^ cofi_vs) ),
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.red_out ( r ),
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.green_out ( g ),
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.blue_out ( b ),
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.hs_out ( hs ),
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.vs_out ( vs ),
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.cs_out ( cs )
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);
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always @(posedge clk_sys) begin
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VGA_R <= r;
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VGA_G <= g;
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VGA_B <= b;
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// a minimig vga->scart cable expects a composite sync signal on the VGA_HS output.
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// and VCC on VGA_VS (to switch into rgb mode)
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VGA_HS <= ((~no_csync & scandoubler_disable) || ypbpr)? cs : hs;
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VGA_VS <= ((~no_csync & scandoubler_disable) || ypbpr)? 1'b1 : vs;
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end
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endmodule
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