104 lines
1.9 KiB
Verilog
104 lines
1.9 KiB
Verilog
// Multiplier-based RGB -> YPbPr conversion
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// Copyright 2020/2021 by Alastair M. Robinson
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module RGBtoYPbPr
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(
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input clk,
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input ena,
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input [WIDTH-1:0] red_in,
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input [WIDTH-1:0] green_in,
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input [WIDTH-1:0] blue_in,
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input hs_in,
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input vs_in,
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input cs_in,
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input pixel_in,
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output [WIDTH-1:0] red_out,
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output [WIDTH-1:0] green_out,
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output [WIDTH-1:0] blue_out,
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output reg hs_out,
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output reg vs_out,
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output reg cs_out,
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output reg pixel_out
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);
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parameter WIDTH = 8;
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reg [8+WIDTH-1:0] r_y;
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reg [8+WIDTH-1:0] g_y;
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reg [8+WIDTH-1:0] b_y;
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reg [8+WIDTH-1:0] r_b;
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reg [8+WIDTH-1:0] g_b;
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reg [8+WIDTH-1:0] b_b;
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reg [8+WIDTH-1:0] r_r;
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reg [8+WIDTH-1:0] g_r;
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reg [8+WIDTH-1:0] b_r;
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reg [8+WIDTH-1:0] y;
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reg [8+WIDTH-1:0] b;
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reg [8+WIDTH-1:0] r;
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reg hs_d;
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reg vs_d;
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reg cs_d;
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reg pixel_d;
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assign red_out = r[8+WIDTH-1:8];
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assign green_out = y[8+WIDTH-1:8];
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assign blue_out = b[8+WIDTH-1:8];
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// Multiply in the first stage...
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always @(posedge clk) begin
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hs_d <= hs_in; // Register sync, pixel clock, etc
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vs_d <= vs_in; // so they're delayed the same amount as the incoming video
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cs_d <= cs_in;
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pixel_d <= pixel_in;
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if(ena) begin
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// (Y = 0.299*R + 0.587*G + 0.114*B)
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r_y <= red_in * 8'd76;
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g_y <= green_in * 8'd150;
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b_y <= blue_in * 8'd29;
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// (Pb = -0.169*R - 0.331*G + 0.500*B)
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r_b <= red_in * 8'd43;
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g_b <= green_in * 8'd84;
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b_b <= blue_in * 8'd128;
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// (Pr = 0.500*R - 0.419*G - 0.081*B)
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r_r <= red_in * 8'd128;
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g_r <= green_in * 8'd107;
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b_r <= blue_in * 8'd20;
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end else begin
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r_r[8+WIDTH-1:8] <= red_in; // Passthrough
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g_y[8+WIDTH-1:8] <= green_in;
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b_b[8+WIDTH-1:8] <= blue_in;
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end
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end
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// Second stage - adding
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always @(posedge clk) begin
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hs_out <= hs_d;
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vs_out <= vs_d;
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cs_out <= cs_d;
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pixel_out <= pixel_d;
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if(ena) begin
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y <= r_y + g_y + b_y;
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b <= 2'd2**(8+WIDTH-1) + b_b - r_b - g_b;
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r <= 2'd2**(8+WIDTH-1) + r_r - g_r - b_r;
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end else begin
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y <= g_y; // Passthrough
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b <= b_b;
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r <= r_r;
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end
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end
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endmodule
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