492 lines
12 KiB
Verilog
492 lines
12 KiB
Verilog
//
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// mist_io.v
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//
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// mist_io for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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//
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// Use buffer to access SD card. It's time-critical part.
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// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
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// (Sorgelig)
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//
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// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
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// clk_ps2 = clk_sys/(PS2DIV*2)
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//
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module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
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(
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// parameter STRLEN and the actual length of conf_str have to match
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input [(8*STRLEN)-1:0] conf_str,
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// Global clock. It should be around 100MHz (higher is better).
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input clk_sys,
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// Global SPI clock from ARM. 24MHz
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input SPI_SCK,
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input CONF_DATA0,
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input SPI_SS2,
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output SPI_DO,
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input SPI_DI,
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output reg [7:0] joystick_0,
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output reg [7:0] joystick_1,
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output reg [15:0] joystick_analog_0,
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output reg [15:0] joystick_analog_1,
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output [1:0] buttons,
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output [1:0] switches,
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output scandoubler_disable,
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output ypbpr,
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output reg [31:0] status,
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// SD config
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input sd_conf,
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input sd_sdhc,
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output img_mounted, // signaling that new image has been mounted
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output reg [31:0] img_size, // size of image in bytes
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// SD block level access
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input [31:0] sd_lba,
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input sd_rd,
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input sd_wr,
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output reg sd_ack,
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output reg sd_ack_conf,
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// SD byte level access. Signals for 2-PORT altsyncram.
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output reg [8:0] sd_buff_addr,
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output reg [7:0] sd_buff_dout,
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input [7:0] sd_buff_din,
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output reg sd_buff_wr,
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// ps2 keyboard emulation
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output ps2_kbd_clk,
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output reg ps2_kbd_data,
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output ps2_mouse_clk,
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output reg ps2_mouse_data,
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input ps2_caps_led,
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// ARM -> FPGA download
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output reg ioctl_download = 0, // signal indicating an active download
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output reg [7:0] ioctl_index, // menu index used to upload the file
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output ioctl_wr,
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output reg [24:0] ioctl_addr,
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output reg [7:0] ioctl_dout
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);
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reg [7:0] b_data;
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reg [6:0] sbuf;
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reg [7:0] cmd;
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reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
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reg [9:0] byte_cnt; // counts bytes
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reg [7:0] but_sw;
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reg [2:0] stick_idx;
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reg mount_strobe = 0;
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assign img_mounted = mount_strobe;
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assign buttons = but_sw[1:0];
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assign switches = but_sw[3:2];
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assign scandoubler_disable = but_sw[4];
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assign ypbpr = but_sw[5];
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wire [7:0] spi_dout = { sbuf, SPI_DI};
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// this variant of user_io is for 8 bit cores (type == a4) only
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wire [7:0] core_type = 8'ha4;
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// command byte read by the io controller
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wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
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reg spi_do;
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assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
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wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
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// drive MISO only when transmitting core id
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always@(negedge SPI_SCK) begin
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if(!CONF_DATA0) begin
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// first byte returned is always core type, further bytes are
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// command dependent
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if(byte_cnt == 0) begin
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spi_do <= core_type[~bit_cnt];
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end else begin
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case(cmd)
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// reading config string
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8'h14: begin
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// returning a byte from string
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if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
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else spi_do <= 0;
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end
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// reading sd card status
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8'h16: begin
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if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
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else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
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else spi_do <= 0;
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end
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// reading sd card write data
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8'h18:
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spi_do <= b_data[~bit_cnt];
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// reading keyboard LED status
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8'h1f:
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spi_do <= kbd_led[~bit_cnt];
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default:
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spi_do <= 0;
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endcase
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end
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end
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end
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reg b_wr2,b_wr3;
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always @(negedge clk_sys) begin
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b_wr3 <= b_wr2;
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sd_buff_wr <= b_wr3;
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end
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// SPI receiver
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always@(posedge SPI_SCK or posedge CONF_DATA0) begin
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if(CONF_DATA0) begin
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b_wr2 <= 0;
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bit_cnt <= 0;
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byte_cnt <= 0;
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sd_ack <= 0;
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sd_ack_conf <= 0;
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end else begin
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b_wr2 <= 0;
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sbuf <= spi_dout[6:0];
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bit_cnt <= bit_cnt + 1'd1;
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if(bit_cnt == 5) begin
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if (byte_cnt == 0) sd_buff_addr <= 0;
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if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
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if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
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end
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// finished reading command byte
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if(bit_cnt == 7) begin
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if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
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if(byte_cnt == 0) begin
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cmd <= spi_dout;
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if(spi_dout == 8'h19) begin
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sd_ack_conf <= 1;
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sd_buff_addr <= 0;
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end
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if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
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sd_ack <= 1;
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sd_buff_addr <= 0;
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end
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if(spi_dout == 8'h18) b_data <= sd_buff_din;
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mount_strobe <= 0;
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end else begin
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case(cmd)
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// buttons and switches
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8'h01: but_sw <= spi_dout;
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8'h02: joystick_0 <= spi_dout;
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8'h03: joystick_1 <= spi_dout;
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// store incoming ps2 mouse bytes
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8'h04: begin
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ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
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ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
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end
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// store incoming ps2 keyboard bytes
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8'h05: begin
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ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
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ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
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end
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8'h15: status[7:0] <= spi_dout;
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// send SD config IO -> FPGA
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// flag that download begins
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// sd card knows data is config if sd_dout_strobe is asserted
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// with sd_ack still being inactive (low)
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8'h19,
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// send sector IO -> FPGA
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// flag that download begins
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8'h17: begin
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sd_buff_dout <= spi_dout;
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b_wr2 <= 1;
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end
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8'h18: b_data <= sd_buff_din;
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// joystick analog
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8'h1a: begin
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// first byte is joystick index
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if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
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else if(byte_cnt == 2) begin
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// second byte is x axis
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if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
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else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
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end else if(byte_cnt == 3) begin
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// third byte is y axis
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if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
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else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
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end
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end
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// notify image selection
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8'h1c: mount_strobe <= 1;
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// send image info
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8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
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// status, 32bit version
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8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
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default: ;
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endcase
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end
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end
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end
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end
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/////////////////////////////// PS2 ///////////////////////////////
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// 8 byte fifos to store ps2 bytes
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localparam PS2_FIFO_BITS = 3;
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reg clk_ps2;
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always @(negedge clk_sys) begin
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integer cnt;
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cnt <= cnt + 1'd1;
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if(cnt == PS2DIV) begin
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clk_ps2 <= ~clk_ps2;
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cnt <= 0;
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end
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end
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// keyboard
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reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
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reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
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reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
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// ps2 transmitter state machine
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reg [3:0] ps2_kbd_tx_state;
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reg [7:0] ps2_kbd_tx_byte;
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reg ps2_kbd_parity;
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assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
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// ps2 transmitter
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// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
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reg ps2_kbd_r_inc;
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always@(posedge clk_sys) begin
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reg old_clk;
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old_clk <= clk_ps2;
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if(~old_clk & clk_ps2) begin
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ps2_kbd_r_inc <= 0;
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if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
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// transmitter is idle?
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if(ps2_kbd_tx_state == 0) begin
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// data in fifo present?
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if(ps2_kbd_wptr != ps2_kbd_rptr) begin
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// load tx register from fifo
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ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
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ps2_kbd_r_inc <= 1;
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// reset parity
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ps2_kbd_parity <= 1;
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// start transmitter
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ps2_kbd_tx_state <= 1;
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// put start bit on data line
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ps2_kbd_data <= 0; // start bit is 0
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end
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end else begin
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// transmission of 8 data bits
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if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
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ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
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ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
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if(ps2_kbd_tx_byte[0])
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ps2_kbd_parity <= !ps2_kbd_parity;
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end
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// transmission of parity
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if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
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// transmission of stop bit
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if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
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// advance state machine
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if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
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else ps2_kbd_tx_state <= 0;
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end
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end
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end
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// mouse
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reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
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reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
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reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
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// ps2 transmitter state machine
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reg [3:0] ps2_mouse_tx_state;
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reg [7:0] ps2_mouse_tx_byte;
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reg ps2_mouse_parity;
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assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
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// ps2 transmitter
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// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
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reg ps2_mouse_r_inc;
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always@(posedge clk_sys) begin
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reg old_clk;
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old_clk <= clk_ps2;
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if(~old_clk & clk_ps2) begin
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ps2_mouse_r_inc <= 0;
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if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
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// transmitter is idle?
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if(ps2_mouse_tx_state == 0) begin
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// data in fifo present?
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if(ps2_mouse_wptr != ps2_mouse_rptr) begin
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// load tx register from fifo
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ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
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ps2_mouse_r_inc <= 1;
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// reset parity
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ps2_mouse_parity <= 1;
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// start transmitter
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ps2_mouse_tx_state <= 1;
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// put start bit on data line
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ps2_mouse_data <= 0; // start bit is 0
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end
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end else begin
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// transmission of 8 data bits
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if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
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ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
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ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
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if(ps2_mouse_tx_byte[0])
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ps2_mouse_parity <= !ps2_mouse_parity;
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end
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// transmission of parity
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if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
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// transmission of stop bit
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if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
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// advance state machine
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if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
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else ps2_mouse_tx_state <= 0;
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end
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end
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end
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/////////////////////////////// DOWNLOADING ///////////////////////////////
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reg [7:0] data_w;
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reg [24:0] addr_w;
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reg rclk = 0;
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localparam UIO_FILE_TX = 8'h53;
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localparam UIO_FILE_TX_DAT = 8'h54;
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localparam UIO_FILE_INDEX = 8'h55;
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// data_io has its own SPI interface to the io controller
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always@(posedge SPI_SCK, posedge SPI_SS2) begin
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reg [6:0] sbuf;
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reg [7:0] cmd;
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reg [4:0] cnt;
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reg [24:0] addr;
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if(SPI_SS2) cnt <= 0;
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else begin
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rclk <= 0;
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// don't shift in last bit. It is evaluated directly
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// when writing to ram
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if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
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// increase target address after write
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if(rclk) addr <= addr + 1'd1;
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// count 0-7 8-15 8-15 ...
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if(cnt < 15) cnt <= cnt + 1'd1;
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else cnt <= 8;
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// finished command byte
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if(cnt == 7) cmd <= {sbuf, SPI_DI};
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// prepare/end transmission
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if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
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// prepare
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if(SPI_DI) begin
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addr <= 0;
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ioctl_download <= 1;
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end else begin
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addr_w <= addr;
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ioctl_download <= 0;
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end
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end
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// command 0x54: UIO_FILE_TX
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if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
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addr_w <= addr;
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data_w <= {sbuf, SPI_DI};
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rclk <= 1;
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end
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// expose file (menu) index
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if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
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end
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end
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assign ioctl_wr = |ioctl_wrd;
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reg [1:0] ioctl_wrd;
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always@(negedge clk_sys) begin
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reg rclkD, rclkD2;
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rclkD <= rclk;
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rclkD2 <= rclkD;
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ioctl_wrd<= {ioctl_wrd[0],1'b0};
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if(rclkD & ~rclkD2) begin
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ioctl_dout <= data_w;
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ioctl_addr <= addr_w;
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ioctl_wrd <= 2'b11;
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end
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end
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endmodule
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