243 lines
7.5 KiB
Systemverilog
243 lines
7.5 KiB
Systemverilog
//
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//
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// Copyright (c) 2017 Sorgelig
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//
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// This program is GPL Licensed. See COPYING for the full license.
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//
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//
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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//
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// LINE_LENGTH: Length of display line in pixels
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// Usually it's length from HSync to HSync.
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// May be less if line_start is used.
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//
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// HALF_DEPTH: If =1 then color dept is 3 bits per component
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// For half depth 6 bits monochrome is available with
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// mono signal enabled and color = {G, R}
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module video_mixer
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#(
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parameter LINE_LENGTH = 768,
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parameter HALF_DEPTH = 0,
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parameter OSD_COLOR = 3'd4,
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parameter OSD_X_OFFSET = 10'd0,
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parameter OSD_Y_OFFSET = 10'd0
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)
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(
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// master clock
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// it should be multiple by (ce_pix*4).
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input clk_sys,
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// Pixel clock or clock_enable (both are accepted).
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input ce_pix,
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// Some systems have multiple resolutions.
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// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
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// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
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// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
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input ce_pix_actual,
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// OSD SPI interface
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input SPI_SCK,
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input SPI_SS3,
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input SPI_DI,
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// scanlines (00-none 01-25% 10-50% 11-75%)
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input [1:0] scanlines,
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// 0 = HVSync 31KHz, 1 = CSync 15KHz
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input scandoubler_disable,
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// High quality 2x scaling
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input hq2x,
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// YPbPr always uses composite sync
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input ypbpr,
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// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
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input ypbpr_full,
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// color
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input [DWIDTH:0] R,
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input [DWIDTH:0] G,
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input [DWIDTH:0] B,
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// Monochrome mode (for HALF_DEPTH only)
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input mono,
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// interlace sync. Positive pulses.
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input HSync,
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input VSync,
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// Falling of this signal means start of informative part of line.
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// It can be horizontal blank signal.
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// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
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// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
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// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
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// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
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// before first informative pixel.
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input line_start,
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// MiST video output signals
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_VS,
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output VGA_HS
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);
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localparam DWIDTH = HALF_DEPTH ? 2 : 5;
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wire [DWIDTH:0] R_sd;
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wire [DWIDTH:0] G_sd;
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wire [DWIDTH:0] B_sd;
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wire hs_sd, vs_sd;
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scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
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(
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.*,
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.hs_in(HSync),
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.vs_in(VSync),
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.r_in(R),
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.g_in(G),
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.b_in(B),
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.hs_out(hs_sd),
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.vs_out(vs_sd),
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.r_out(R_sd),
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.g_out(G_sd),
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.b_out(B_sd)
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);
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wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
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wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
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wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
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generate
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if(HALF_DEPTH) begin
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wire [5:0] r = mono ? {gt,rt} : {rt,rt};
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wire [5:0] g = mono ? {gt,rt} : {gt,gt};
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wire [5:0] b = mono ? {gt,rt} : {bt,bt};
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end else begin
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wire [5:0] r = rt;
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wire [5:0] g = gt;
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wire [5:0] b = bt;
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end
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endgenerate
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wire hs = (scandoubler_disable ? HSync : hs_sd);
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wire vs = (scandoubler_disable ? VSync : vs_sd);
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reg scanline = 0;
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always @(posedge clk_sys) begin
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reg old_hs, old_vs;
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old_hs <= hs;
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old_vs <= vs;
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if(old_hs && ~hs) scanline <= ~scanline;
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if(old_vs && ~vs) scanline <= 0;
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end
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wire [5:0] r_out, g_out, b_out;
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always @(*) begin
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case(scanlines & {scanline, scanline})
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1: begin // reduce 25% = 1/2 + 1/4
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r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
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g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
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b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
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end
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2: begin // reduce 50% = 1/2
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r_out = {1'b0, r[5:1]};
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g_out = {1'b0, g[5:1]};
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b_out = {1'b0, b[5:1]};
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end
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3: begin // reduce 75% = 1/4
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r_out = {2'b00, r[5:2]};
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g_out = {2'b00, g[5:2]};
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b_out = {2'b00, b[5:2]};
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end
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default: begin
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r_out = r;
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g_out = g;
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b_out = b;
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end
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endcase
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end
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wire [5:0] red, green, blue;
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osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
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(
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.*,
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.R_in(r_out),
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.G_in(g_out),
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.B_in(b_out),
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.HSync(hs),
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.VSync(vs),
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.R_out(red),
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.G_out(green),
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.B_out(blue)
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);
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wire [5:0] yuv_full[225] = '{
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6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
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6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
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6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
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6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
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6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
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6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
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6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
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6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
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6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
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6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
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6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
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6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
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6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
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6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
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6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
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6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
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6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
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6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
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6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
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6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
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6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
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6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
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6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
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6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
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6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
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6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
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6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
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6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
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6'd63
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};
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// http://marsee101.blog19.fc2.com/blog-entry-2311.html
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// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
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// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
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// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
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wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
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wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
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wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
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wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
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wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
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wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
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assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
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assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
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assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
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assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
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assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
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endmodule
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