123 lines
3.2 KiB
Verilog
123 lines
3.2 KiB
Verilog
module tm1638(
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input clk,
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input clk_en,
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input rst,
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input data_latch,
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inout [7:0] data,
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input rw,
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output busy,
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output sclk,
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input dio_in,
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output reg dio_out
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);
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localparam CLK_DIV = 3; // seems happy at 12MHz with 3
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localparam CLK_DIV1 = CLK_DIV - 1;
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localparam [1:0]
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S_IDLE = 2'h0,
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S_WAIT = 2'h1,
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S_TRANSFER = 2'h2;
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reg [1:0] cur_state, next_state;
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reg [CLK_DIV1:0] sclk_d, sclk_q;
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reg [7:0] data_d, data_q, data_out_d, data_out_q;
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reg dio_out_d;
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reg [2:0] ctr_d, ctr_q;
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// output read data if we're reading
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assign data = rw ? 8'hZZ : data_out_q;
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// we're busy if we're not idle
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assign busy = cur_state != S_IDLE;
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// tick the clock if we're transfering data
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assign sclk = ~((~sclk_q[CLK_DIV1]) & (cur_state == S_TRANSFER));
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always @(*)
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begin
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sclk_d = sclk_q;
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data_d = data_q;
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dio_out_d = dio_out;
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ctr_d = ctr_q;
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data_out_d = data_out_q;
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next_state = cur_state;
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case(cur_state)
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S_IDLE: begin
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sclk_d = 0;
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if (data_latch) begin
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// if we're reading, set to zero, otherwise latch in
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// data to send
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data_d = rw ? data : 8'b0;
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next_state = S_WAIT;
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end
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end
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S_WAIT: begin
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sclk_d = sclk_q + 1;
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// wait till we're halfway into clock pulse
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if (sclk_q == {1'b0, {CLK_DIV1{1'b1}}}) begin
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sclk_d = 0;
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next_state = S_TRANSFER;
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end
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end
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S_TRANSFER: begin
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sclk_d = sclk_q + 1;
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if (sclk_q == 0) begin
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// start of clock pulse, output MSB
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dio_out_d = data_q[0];
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end else if (sclk_q == {1'b0, {CLK_DIV1{1'b1}}}) begin
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// halfway through pulse, read from device
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data_d = {dio_in, data_q[7:1]};
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end else if (&sclk_q) begin
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// end of pulse, tick the counter
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ctr_d = ctr_q + 1;
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if (&ctr_q) begin
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// last bit sent, switch back to idle
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// and output any data recieved
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next_state = S_IDLE;
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data_out_d = data_q;
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dio_out_d = 0;
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end
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end
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end
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default:
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next_state = S_IDLE;
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endcase
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end
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always @(posedge clk)
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begin
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if (clk_en)
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begin
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if (rst)
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begin
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cur_state <= S_IDLE;
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sclk_q <= 0;
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ctr_q <= 0;
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dio_out <= 0;
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data_q <= 0;
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data_out_q <= 0;
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end
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else
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begin
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cur_state <= next_state;
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sclk_q <= sclk_d;
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ctr_q <= ctr_d;
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dio_out <= dio_out_d;
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data_q <= data_d;
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data_out_q <= data_out_d;
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end
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end
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end
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endmodule
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