340 lines
15 KiB
Verilog
340 lines
15 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: PS/2 keyboard interface
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//
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// Author.....: Niels A. Moseley
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// Date.......: 28-1-2018
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//
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module ps2keyboard (
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input clk14, // 25MHz clock
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input rst, // active high reset
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// I/O interface to keyboard
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input key_clk, // clock input from keyboard / device
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input key_din, // data input from keyboard / device
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// I/O interface to computer
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input cs, // chip select, active high
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input address, // =0 RX buffer, =1 RX status
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output reg [7:0] dout // 8-bit output bus.
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);
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reg [3:0] rxcnt; // count how many bits have been shift into rxshiftbuf
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reg [10:0] rxshiftbuf; // 11 bit shift receive register
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reg rx_flag = 0; // this flag is 1 when
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// valid data is available in rxshiftbuf
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reg [7:0] rx; // scancode receive buffer
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// wire ps2_clkdb; // debounced PS/2 clock signal
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reg prev_ps2_clkdb; // previous clock state (in clk14 domain)
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// keyboard translation signals
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reg [7:0] ascii; // ASCII code of received character
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reg ascii_rdy; // new ASCII character received
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reg shift; // state of the shift key
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reg [2:0] cur_state;
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reg [2:0] next_state;
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// debounce ps2clk_debounce
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// (
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// .clk14(clk14),
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// .rst(rst),
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// .sig_in(key_clk),
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// .sig_out(ps2_clkdb)
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// );
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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begin
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prev_ps2_clkdb <= 1'b0;
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rx_flag <= 1'b0;
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end
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else
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begin
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rx_flag <= 1'b0; // reset the new data flag register
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// check for negative edge of PS/2 clock
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// and sample the state of the PS/2 data line
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if ((prev_ps2_clkdb == 1'b1) && (key_clk == 1'b0))//(ps2_clkdb == 1'b0))
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begin
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rxshiftbuf <= {key_din, rxshiftbuf[10:1]};
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rxcnt <= rxcnt + 4'b1;
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if (rxcnt == 4'd10)
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begin
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// 10 bits have been shifted in
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// we should have a complete
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// scan code here, including
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// start, parity and stop bits.
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rxcnt <= 0;
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// signal new data is present
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// note: this signal will only remain high for one
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// clock cycle!
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//
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// TODO: check parity here?
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rx_flag <= 1'b1;
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end
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end
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// update previous clock state
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prev_ps2_clkdb <= key_clk;//ps2_clkdb;
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end
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end
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//
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// IBM Keyboard code page translation
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// state machine for US keyboard layout
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//
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// http://www.computer-engineering.org/ps2keyboard/scancodes2.html
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//
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localparam S_KEYNORMAL = 3'b000;
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localparam S_KEYF0 = 3'b001; // regular key release state
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localparam S_KEYE0 = 3'b010; // extended key state
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localparam S_KEYE0F0 = 3'b011; // extended release state
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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begin
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rx <= 0;
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ascii_rdy <= 0;
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shift <= 0;
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cur_state <= S_KEYNORMAL;
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end
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else
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begin
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// handle I/O from CPU
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if (cs == 1'b1)
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begin
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if (address == 1'b0)
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begin
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// RX buffer address
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dout <= {1'b1, ascii[6:0]};
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ascii_rdy <= 1'b0;
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end
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else
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begin
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// RX status register
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dout <= {ascii_rdy, 7'b0};
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end
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end
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// keyboard translation state machine
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if (rx_flag == 1'b1)
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begin
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// latch data from the serial buffer into
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// the rx scancode buffer.
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rx <= rxshiftbuf[8:1];
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case(cur_state)
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S_KEYNORMAL:
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begin
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if (rx == 8'hF0)
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next_state = S_KEYF0;
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else if (rx == 8'hE0)
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next_state = S_KEYE0;
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else
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begin
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// check the debounce timer, if this is
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// not zero, a new key arrived too quickly
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// and we simply discard it. For better
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// debouncing, we should check if the key
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// is actually the same as the previous received/
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// key, but let's try this first to see if it works
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// ok...
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//if (debounce_timer == 16'd0)
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//begin
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ascii_rdy <= 1'b1; // new key has arrived!
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//debounce_timer <= 16'hFFFF; // reset the debounce timer
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//end
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// check for a SHIFT key
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if ((rx == 8'h59) || (rx == 8'h12))
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begin
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shift <= 1'b1;
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ascii_rdy <= 1'b0; // shift is not a key!
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end
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else begin
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if (!shift)
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case(rx)
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8'h1C: ascii <= "A";
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8'h32: ascii <= "B";
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8'h21: ascii <= "C";
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8'h23: ascii <= "D";
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8'h24: ascii <= "E";
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8'h2B: ascii <= "F";
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8'h34: ascii <= "G";
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8'h33: ascii <= "H";
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8'h43: ascii <= "I";
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8'h3B: ascii <= "J";
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8'h42: ascii <= "K";
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8'h4B: ascii <= "L";
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8'h3A: ascii <= "M";
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8'h31: ascii <= "N";
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8'h44: ascii <= "O";
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8'h4D: ascii <= "P";
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8'h15: ascii <= "Q";
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8'h2D: ascii <= "R";
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8'h1B: ascii <= "S";
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8'h2C: ascii <= "T";
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8'h3C: ascii <= "U";
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8'h2A: ascii <= "V";
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8'h1D: ascii <= "W";
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8'h22: ascii <= "X";
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8'h35: ascii <= "Y";
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8'h1A: ascii <= "Z";
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8'h45: ascii <= "0";
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8'h16: ascii <= "1";
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8'h1E: ascii <= "2";
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8'h26: ascii <= "3";
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8'h25: ascii <= "4";
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8'h2E: ascii <= "5";
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8'h36: ascii <= "6";
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8'h3D: ascii <= "7";
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8'h3E: ascii <= "8";
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8'h46: ascii <= "9";
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8'h4E: ascii <= "-";
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8'h55: ascii <= "=";
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8'h5D: ascii <= 8'h34; // backslash
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8'h66: ascii <= 8'd8; // backspace
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8'h29: ascii <= " ";
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8'h5A: ascii <= 8'd13; // enter
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8'h54: ascii <= "[";
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8'h5B: ascii <= "]";
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8'h4C: ascii <= ";";
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8'h52: ascii <= "'";
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8'h41: ascii <= ",";
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8'h49: ascii <= ".";
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8'h4A: ascii <= "/";
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default:
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// unsupported key!
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begin
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ascii_rdy <= 1'b0; // shift is not a key!
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ascii <= " ";
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end
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endcase
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else
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// Here, we're in a shifted state
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case(rx)
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8'h1C: ascii <= "A";
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8'h32: ascii <= "B";
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8'h21: ascii <= "C";
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8'h23: ascii <= "D";
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8'h24: ascii <= "E";
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8'h2B: ascii <= "F";
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8'h34: ascii <= "G";
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8'h33: ascii <= "H";
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8'h43: ascii <= "I";
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8'h3B: ascii <= "J";
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8'h42: ascii <= "K";
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8'h4B: ascii <= "L";
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8'h3A: ascii <= "M";
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8'h31: ascii <= "N";
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8'h44: ascii <= "O";
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8'h4D: ascii <= "P";
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8'h15: ascii <= "Q";
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8'h2D: ascii <= "R";
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8'h1B: ascii <= "S";
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8'h2C: ascii <= "T";
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8'h3C: ascii <= "U";
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8'h2A: ascii <= "V";
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8'h1D: ascii <= "W";
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8'h22: ascii <= "X";
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8'h35: ascii <= "Y";
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8'h1A: ascii <= "Z";
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8'h45: ascii <= ")";
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8'h16: ascii <= "!";
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8'h1E: ascii <= "@";
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8'h26: ascii <= "#";
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8'h25: ascii <= "$";
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8'h2E: ascii <= "%";
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8'h36: ascii <= "^";
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8'h3D: ascii <= "&";
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8'h3E: ascii <= "*";
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8'h46: ascii <= "(";
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8'h4E: ascii <= "_";
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8'h55: ascii <= "+";
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8'h5D: ascii <= "|";
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8'h66: ascii <= 8'd8; // backspace
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8'h29: ascii <= " ";
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8'h5A: ascii <= 8'd13; // enter
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8'h54: ascii <= "{";
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8'h5B: ascii <= "}";
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8'h4C: ascii <= ":";
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8'h52: ascii <= "\"";
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8'h41: ascii <= "<";
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8'h49: ascii <= ">";
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8'h4A: ascii <= "?";
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default:
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// unsupported key!
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begin
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ascii_rdy <= 1'b0; // shift is not a key!
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ascii <= " ";
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end
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endcase
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end
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end
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end
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S_KEYF0:
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// when we end up here, a 0xF0 byte was received
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// which usually means a key release event
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begin
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if ((rx == 8'h59) || (rx == 8'h12))
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shift <= 1'b0;
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next_state = S_KEYNORMAL;
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end
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S_KEYE0:
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begin
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if (rx == 8'hF0)
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next_state = S_KEYE0F0;
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else
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next_state = S_KEYNORMAL;
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end
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S_KEYE0F0:
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begin
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next_state = S_KEYNORMAL;
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end
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default:
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begin
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next_state = S_KEYNORMAL;
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end
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endcase
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end
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else
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begin
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next_state = cur_state; // deliberate blocking assingment!
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end
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cur_state <= next_state;
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end
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end
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endmodule
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