56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Clock divider to provide clock enables for
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// devices.
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 29-1-2018
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//
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module pwr_reset(
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input clk14, // 14Mhz master clock
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input rst_n, // active low synchronous reset
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input enable, // clock enable
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output rst // active high synchronous system reset
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);
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reg hard_reset;
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reg [5:0] reset_cnt;
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wire pwr_up_flag = &reset_cnt;
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always @(posedge clk14)
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begin
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if (rst_n == 1'b0)
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begin
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reset_cnt <= 6'b0;
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hard_reset <= 1'b0;
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end
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else if (enable)
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begin
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if (!pwr_up_flag)
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reset_cnt <= reset_cnt + 6'b1;
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hard_reset <= pwr_up_flag;
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end
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end
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assign rst = ~hard_reset;
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endmodule
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