46 lines
1.4 KiB
Verilog
46 lines
1.4 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: 8KB RAM for system
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module ram (
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input clk, // clock signal
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input [12:0] address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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output reg [7:0] dout // 8-bit data bus (output)
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);
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reg [7:0] ram_data[0:8191];
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initial
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$readmemh("roms/ram.hex", ram_data, 0, 8191);
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always @(posedge clk)
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begin
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dout <= ram_data[address];
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if (w_en) ram_data[address] <= din;
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end
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endmodule
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