300 lines
9.1 KiB
Verilog
300 lines
9.1 KiB
Verilog
module vga (
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input clk14, // clock signal
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input enable, // clock enable strobe,
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input rst, // active high reset signal
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output vga_h_sync, // horizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output vga_red, // red VGA signal
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output vga_grn, // green VGA signal
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output vga_blu, // blue VGA signal
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input address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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input [1:0] mode, // 2-bit mode setting for pixel doubling
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input [2:0] fg_colour, // 3 bit background colour
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input [2:0] bg_colour, // 3 bit foreground colour
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input clr_screen // clear screen button
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Parameters
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// video structure constants
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parameter h_pixels = 910; // horizontal pixels per line
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parameter v_lines = 262; // vertical lines per frame
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parameter h_pulse = 65; // hsync pulse length (was: 96)
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parameter v_pulse = 2; // vsync pulse length
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parameter hbp = 144+64; // end of horizontal back porch
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parameter hfp = 784+64; // beginning of horizontal front porch
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parameter vbp = 10+32; // end of vertical back porch
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parameter vfp = 202+32; // beginning of vertical front porch
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// registers for storing the horizontal & vertical counters
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reg [9:0] h_cnt;
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reg [9:0] v_cnt;
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wire [3:0] h_dot;
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reg [4:0] v_dot;
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// hardware cursor registers
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wire [10:0] cursor;
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reg [5:0] h_cursor;
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reg [4:0] v_cursor;
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// vram indexing registers
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reg [5:0] vram_h_addr;
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reg [4:0] vram_v_addr;
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reg [4:0] vram_start_addr;
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reg [4:0] vram_end_addr;
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wire [4:0] vram_clr_addr;
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// vram registers
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wire [10:0] vram_r_addr;
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reg [10:0] vram_w_addr;
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reg vram_w_en;
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reg [5:0] vram_din;
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wire [5:0] vram_dout;
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// font rom registers
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wire [5:0] font_char;
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wire [3:0] font_pixel;
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wire [4:0] font_line;
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wire font_out;
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// cpu control registers
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reg char_seen;
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// active region strobes
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wire h_active;
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wire v_active;
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assign h_active = (h_cnt >= hbp && h_cnt < hfp);
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assign v_active = (v_cnt >= vbp && v_cnt < vfp);
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//////////////////////////////////////////////////////////////////////////
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// VGA Sync Generation
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//
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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begin
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h_cnt <= 10'd0;
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v_cnt <= 10'd0;
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v_dot <= 5'd0;
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end
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else
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begin
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if (h_cnt < h_pixels)
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h_cnt <= h_cnt + 1;
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else
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begin
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// reset horizontal counters
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h_cnt <= 0;
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if (v_cnt < v_lines)
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begin
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v_cnt <= v_cnt + 1;
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// count 20 rows, so 480px / 20 = 24 rows
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if (v_active)
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begin
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v_dot <= v_dot + 1; // +1
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if (v_dot == 5'd7) // == d19
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v_dot <= 0;
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end
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end
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else
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begin
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// reset vertical counters
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v_cnt <= 0;
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v_dot <= 0;
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end
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end
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end
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end
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// count 16 pixels, so 640px / 16 = 40 characters
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assign h_dot = h_active ? h_cnt[3:0] : 4'd0;
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//////////////////////////////////////////////////////////////////////////
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// Character ROM
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font_rom font_rom(
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.clk(clk14),
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.mode(mode),
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.character(font_char),
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.pixel(font_pixel),
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.line(font_line),
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.out(font_out)
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);
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//////////////////////////////////////////////////////////////////////////
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// Video RAM
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vram vram(
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.clk(clk14),
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.read_addr(vram_r_addr),
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.write_addr(vram_w_addr),
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.r_en(h_active),
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.w_en(vram_w_en),
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.din(vram_din),
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.dout(vram_dout)
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);
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//////////////////////////////////////////////////////////////////////////
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// Video Signal Generation
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always @(posedge clk14 or posedge rst) begin
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if (rst) begin
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vram_h_addr <= 'd0;
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vram_v_addr <= 'd0;
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end else begin
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// start the pipeline for reading vram and font details
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// 3 pixel clock cycles early
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if (h_dot == 4'hC)
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vram_h_addr <= vram_h_addr + 'd1;
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// advance to next row when last display line is reached for row
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if (v_dot == 5'd7 && h_cnt == 10'd0) // == d19
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vram_v_addr <= vram_v_addr + 'd1;
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// clear the address registers if we're not in visible area
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if (~h_active)
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vram_h_addr <= 'd0;
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if (~v_active)
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vram_v_addr <= vram_start_addr;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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// Cursor blink
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reg blink;
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reg [22:0] blink_div;
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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blink_div <= 0;
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else
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begin
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blink_div <= blink_div + 1;
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if (blink_div == 23'd0)
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blink <= ~blink;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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// Pipeline and VGA signals
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// vram to font rom to display pipeline assignments
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assign cursor = {v_cursor, h_cursor};
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assign vram_r_addr = {vram_v_addr, vram_h_addr};
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assign font_char = (vram_r_addr != cursor) ? vram_dout : (blink) ? 6'd0 : 6'd32;
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assign font_pixel = h_dot + 1; // offset by one to get pixel into right cycle,
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// font output one pixel clk behind
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assign font_line = v_dot * 2 + 4;
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// vga signals out to monitor
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assign vga_red = (h_active & v_active) ? (font_out ? fg_colour[2] : bg_colour[2]) : 1'b0;
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assign vga_grn = (h_active & v_active) ? (font_out ? fg_colour[1] : bg_colour[1]) : 1'b0;
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assign vga_blu = (h_active & v_active) ? (font_out ? fg_colour[0] : bg_colour[0]) : 1'b0;
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assign vga_h_sync = (h_cnt < h_pulse) ? 0 : 1;
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assign vga_v_sync = (v_cnt < v_pulse) ? 0 : 1;
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//////////////////////////////////////////////////////////////////////////
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// CPU control and hardware cursor
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assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]};
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always @(posedge clk14 or posedge rst)
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begin
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if (rst)
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begin
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h_cursor <= 6'd0;
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v_cursor <= 5'd0;
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char_seen <= 'b0;
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vram_start_addr <= 5'd0;
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vram_end_addr <= 5'd24;
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end
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else
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begin
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vram_w_en <= 0;
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if (clr_screen)
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begin
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// return to top of screen
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h_cursor <= 6'd0;
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v_cursor <= 5'd0;
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vram_start_addr <= 5'd0;
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vram_end_addr <= 5'd24;
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// clear the screen
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vram_w_addr <= {vram_v_addr, vram_h_addr};
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vram_din <= 6'd32;
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vram_w_en <= 1;
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end
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else
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begin
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// cursor overflow handling
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if (h_cursor == 6'd40)
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begin
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h_cursor <= 6'd0;
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v_cursor <= v_cursor + 'd1;
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end
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if (v_cursor == vram_end_addr)
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begin
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vram_start_addr <= vram_start_addr + 'd1;
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vram_end_addr <= vram_end_addr + 'd1;
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end
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if (address == 1'b0) // address low == TX register
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begin
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if (enable & w_en & ~char_seen)
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begin
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// incoming character
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char_seen <= 1;
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case(din)
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8'h0D,
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8'h8D: begin
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// handle carriage return
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h_cursor <= 0;
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v_cursor <= v_cursor + 'd1;
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end
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8'h00,
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8'h0A,
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8'h9B,
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8'h7F: begin
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// ignore the escape key
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h_cursor <= 0;
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end
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default: begin
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vram_w_addr <= cursor;
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vram_din <= {~din[6], din[4:0]};
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vram_w_en <= 1;
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h_cursor <= h_cursor + 1;
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end
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endcase
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end
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else if(~enable & ~w_en)
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char_seen <= 0;
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end
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else
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begin
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vram_w_addr <= {vram_clr_addr, vram_h_addr};
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vram_din <= 6'd32;
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vram_w_en <= 1;
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end
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end
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end
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end
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endmodule
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