659 lines
20 KiB
Systemverilog
659 lines
20 KiB
Systemverilog
// Apple-1 for MiST
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//
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// Forked from Gehstock's implementation https://github.com/Gehstock/Mist_FPGA
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//
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// TODO display: crosstalk artifact (selectable)
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// TODO use a CPU that allows illegal instructions
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// TODO power on-off key ? init ram with values
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// TODO ram powerup initial values
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// TODO reorganize file structure
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// TODO ACI: wav tools
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// TODO A-F chip selection banks?
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// TODO check diff with updated data_io.v and other modules
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// TODO keyboard: use a PIA
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// TODO keyboard: isolate ps2 keyboard from apple1
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// TODO keyboard: check ps2 clock
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// TODO keyboard: make a true ascii keyboard
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// TODO osd menu yellow, why it doesn't work?
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// TODO display: check NTSC AD724 hsync problem
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// TODO display: powerup values
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// TODO display: simplify rom font
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// TODO display: reduce to 512 bytes font
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// TODO display: check parameters vs real apple1
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// TODO display: check cursor blinking vs 555 timings
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// TODO display: emulate PIA registers
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// TODO tms9918: fix video sync on composite and mist_video
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// TODO tms9918: make it selectable / use include in code
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// TODO sid: implement 6581
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// *TODO make it work with SDRAM
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module apple1_mist(
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input CLOCK_27,
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// SPI interface to arm io controller
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input SPI_SCK,
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output SPI_DO,
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input SPI_DI,
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input SPI_SS2,
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input SPI_SS3,
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input SPI_SS4,
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input CONF_DATA0,
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// SDRAM interface
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inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
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output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits
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output SDRAM_DQML, // SDRAM Low-byte Data Mask
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output SDRAM_DQMH, // SDRAM High-byte Data Mask
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output SDRAM_nWE, // SDRAM Write Enable
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output SDRAM_nCAS, // SDRAM Column Address Strobe
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output SDRAM_nRAS, // SDRAM Row Address Strobe
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output SDRAM_nCS, // SDRAM Chip Select
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output [1:0] SDRAM_BA, // SDRAM Bank Address
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output SDRAM_CLK, // SDRAM Clock
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output SDRAM_CKE, // SDRAM Clock Enable
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// VGA interface
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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// other
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output LED,
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input UART_RX,
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output AUDIO_L,
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output AUDIO_R
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);
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`include "rtl\build_id.v"
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @user_io ***************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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localparam CONF_STR = {
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"APPLE 1;;", // 0 download index for "apple1.rom"
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"F,PRG,Load program;", // 1 download index for ".prg" files
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"O2,TMS9918 output,Off,On;",
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"O3,Audio monitor,tape in,tape out;",
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"T6,Reset (F5);",
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"V,v1.01.",`BUILD_DATE
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};
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localparam conf_str_len = $size(CONF_STR)>>3;
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wire st_reset_switch = buttons[1];
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wire r, g, b;
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wire hs, vs;
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire st_tms9918_output = status[2];
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wire st_audio_mon_tape_in = ~status[3];
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wire st_menu_reset = status[6];
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wire scandoubler_disable;
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wire ypbpr;
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wire no_csync;
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wire ps2_kbd_clk;
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wire ps2_kbd_data;
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wire reset_button = status[0] | st_menu_reset | st_reset_switch | reset_key_edge |!pll_locked;
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @pll *******************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire pll_locked;
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wire sys_clock; // cpu x 7 x 8 system clock (sdram.v)
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wire osd_clock; // cpu x 7 x 2 for the OSD menu
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wire vdp_clock; // tms9918 x 2 for osd menu
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pll pll
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(
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.inclk0(CLOCK_27),
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.locked(pll_locked),
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.c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu
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.c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v)
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.c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns
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.c4( vdp_clock ) // tms9918 x 2 for osd menu (10.738635 x 2 = 21.47727)
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @downloader ************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire is_downloading; // indicates that downloader is working
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wire [24:0] download_addr; // download address
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wire [7:0] download_data; // download data
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wire download_wr; // download write enable
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wire ROM_loaded; // 1 when boot rom has been downloaded
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// ROM download helper
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downloader
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#(
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.BOOT_INDEX (0), // menu index 0 is for automatic download of "apple1.rom" at FPGA boot
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.PRG_INDEX (1), // menu index for load .prg
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.ROM_INDEX (2), // menu index for load .prg
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.ROM_START_ADDR(0) // start of ROM (bank 0 of SDRAM)
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)
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downloader
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(
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// new SPI interface
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.SPI_DO ( SPI_DO ),
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.SPI_DI ( SPI_DI ),
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.SPI_SCK( SPI_SCK ),
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.SPI_SS2( SPI_SS2 ),
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.SPI_SS3( SPI_SS3 ),
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.SPI_SS4( SPI_SS4 ),
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// signal indicating an active rom download
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.downloading ( is_downloading ),
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.ROM_done ( ROM_loaded ),
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// external ram interface
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.clk ( sys_clock ),
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.clk_ena ( cpu_clken_noRF ),
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.wr ( download_wr ),
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.addr ( download_addr ),
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.data ( download_data )
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @ram *******************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire [7:0] ram_dout;
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// low system RAM
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ram #(.SIZE(16384)) ram(
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.clk (sys_clock ),
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.address(sdram_addr[15:0]),
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.w_en (sdram_wr & ram_cs),
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.din (sdram_din ),
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.dout (ram_dout )
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);
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// WozMon ROM
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wire [7:0] rom_dout;
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rom_wozmon rom_wozmon(
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.clk(sys_clock),
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.address(cpu_addr[7:0]),
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.dout(rom_dout)
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);
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// Basic RAM
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wire [7:0] basic_dout;
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ram #(.SIZE(4096)) rom_basic(
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.clk(sys_clock),
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.address({4'b000, sdram_addr[11:0]}),
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.w_en (sdram_wr & basic_cs),
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.din (sdram_din ),
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.dout (basic_dout)
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @ACI *******************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire [7:0] aci_dout;
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wire CASOUT;
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ACI ACI(
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.clk(sys_clock),
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.cpu_clken(cpu_clken),
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.addr(sdram_addr[15:0]),
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.dout(aci_dout),
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.tape_in(CASIN),
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.tape_out(CASOUT),
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);
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// latches cassette audio input
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reg CASIN;
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always @(posedge sys_clock) begin
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CASIN <= ~UART_RX; // on the Mistica UART_RX is the audio input
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end
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wire audio;
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wire audio_monitor = st_audio_mon_tape_in ? CASIN : CASOUT ;
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dac #(.C_bits(16)) dac_AUDIO
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(
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.clk_i(sys_clock),
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.res_n_i(pll_locked),
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.dac_i({ audio_monitor, 15'b0000000 }),
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.dac_o(audio)
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);
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always @(posedge sys_clock) begin
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AUDIO_L <= audio;
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AUDIO_R <= audio;
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end
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @apple1 ****************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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// SDRAM control signals
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wire [24:0] sdram_addr;
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wire [7:0] sdram_din;
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wire sdram_wr;
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wire sdram_rd;
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wire [7:0] sdram_dout;
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always @(*) begin
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if(is_downloading && download_wr) begin
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sdram_addr <= download_addr;
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sdram_din <= download_data;
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sdram_wr <= download_wr;
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sdram_rd <= 1'b1;
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end
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else begin
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sdram_addr <= { 9'b0, cpu_addr[15:0] };
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sdram_din <= cpu_dout;
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sdram_wr <= cpu_wr;
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sdram_rd <= 1'b1;
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end
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end
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wire dummy = is_downloading && download_wr;
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assign LED = ~dummy;
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// ram interface
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wire [15:0] cpu_addr;
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wire [7:0] cpu_dout;
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wire cpu_rd;
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wire cpu_wr;
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wire ram_cs = sdram_addr < 'h4000; // 0x0000 -> 0x3FFF
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wire sdram_cs = sdram_addr >= 'h4000 && sdram_addr <= 'hBFFF; // 0x4000 -> 0xBFFF
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wire aci_cs = sdram_addr >= 'hC000 && sdram_addr <= 'hC1FF; // 0xC000 -> 0xC1FF
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wire tms_cs = sdram_addr >= 'hCC00 && sdram_addr <= 'hCC01; // 0xCC00 -> 0xCC01
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wire basic_cs = sdram_addr >= 'hE000 && sdram_addr <= 'hEFFF; // 0xE000 -> 0xEFFF
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wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFFF
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wire [7:0] bus_dout = rom_cs ? rom_dout :
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basic_cs ? basic_dout :
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tms_cs ? vdp_dout :
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aci_cs ? aci_dout :
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sdram_cs ? sdram_dout :
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ram_cs ? ram_dout :
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8'b0;
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wire reset_key;
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wire poweroff_key;
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// detects the rising edge of the keyboard reset key
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// otherwise keyboard stays in reset mode
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wire reset_key_edge = reset_key_old == 0 && reset_key == 1;
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reg reset_key_old = 0;
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always @(posedge sys_clock) begin
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reset_key_old <= reset_key;
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end
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apple1 apple1
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(
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.reset(reset_button),
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.sys_clock ( sys_clock ), // system clock
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.cpu_clken ( cpu_clken ), // CPU clock enable
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.pixel_clken ( pixel_clken ), // pixel clock enable
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// RAM interface
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.ram_addr (cpu_addr),
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.ram_din (cpu_dout),
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.ram_dout (bus_dout),
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.ram_rd (cpu_rd),
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.ram_wr (cpu_wr),
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// ps2 keyboard
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.ps2_clk(ps2_kbd_clk),
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.ps2_din(ps2_kbd_data),
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// interrupt signal
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.INT_n(VDP_INT_n),
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.vga_h_sync(hs),
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.vga_v_sync(vs),
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.vga_red(r),
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.vga_grn(g),
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.vga_blu(b),
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.vga_cls(), // clear screen button (not connected yet)
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.reset_key(reset_key), // keyboard shortcut for reset
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.poweroff_key(poweroff_key) // keyboard shortcut for power off/on
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @mist_video ************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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mist_video
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#(
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.COLOR_DEPTH(1), // 1 bit color depth
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.OSD_AUTO_CE(1), // OSD autodetects clock enable
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.OSD_COLOR(3'b110), // yellow menu color
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.SYNC_AND(1),
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.SD_HCNT_WIDTH(11)
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)
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mist_video
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(
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.clk_sys(osd_clock), // OSD needs 2x the VDP clock for the scandoubler
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// OSD SPI interface
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.SPI_DI(SPI_DI),
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.SPI_SCK(SPI_SCK),
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.SPI_SS3(SPI_SS3),
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.scanlines(2'b00), // scanline emulation disabled for now
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.ce_divider(1), // non-scandoubled pixel clock divider 0 - clk_sys/4, 1 - clk_sys/2
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.scandoubler_disable(scandoubler_disable), // disable scandoubler option from mist.ini
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.no_csync(no_csync), // csync option from mist.ini
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.ypbpr(ypbpr), // YPbPr option from mist.ini
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.rotate(2'b00), // no ODS rotation
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.blend(0), // composite-like blending
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// video input signals to mist_video
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.R(r),
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.G(g),
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.B(b),
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.HSync(hs),
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.VSync(vs),
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// video output signals that go into MiST hardware
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.VGA_R(apple1_R),
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.VGA_G(apple1_G),
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.VGA_B(apple1_B),
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.VGA_VS(apple1_VS),
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.VGA_HS(apple1_HS)
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);
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wire [5:0] apple1_R;
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wire [5:0] apple1_G;
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wire [5:0] apple1_B;
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wire apple1_HS;
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wire apple1_VS;
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// mix video
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assign VGA_R = st_tms9918_output ? tms_R : apple1_R ;
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assign VGA_G = st_tms9918_output ? tms_G : apple1_G ;
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assign VGA_B = st_tms9918_output ? tms_B : apple1_B ;
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assign VGA_HS = st_tms9918_output ? tms_HS & tms_VS : apple1_HS;
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assign VGA_VS = st_tms9918_output ? tms_VS : apple1_VS;
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wire [5:0] tms_out_R;
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wire [5:0] tms_out_G;
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wire [5:0] tms_out_B;
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wire tms_out_HS;
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wire tms_out_VS;
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mist_video
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#(
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.COLOR_DEPTH(6), // 1 bit color depth
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.OSD_AUTO_CE(1), // OSD autodetects clock enable
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.OSD_COLOR(3'b110), // yellow menu color
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.SYNC_AND(1),
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.SD_HCNT_WIDTH(11)
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)
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tms_mist_video
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(
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//.clk_sys(vdp_clock), // OSD needs 2x the VDP clock for the scandoubler
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.clk_sys(osd_clock),
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// OSD SPI interface
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.SPI_DI(SPI_DI),
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.SPI_SCK(SPI_SCK),
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.SPI_SS3(SPI_SS3),
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.scanlines(2'b00), // scanline emulation disabled for now
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.ce_divider(1), // non-scandoubled pixel clock divider 0 - clk_sys/4, 1 - clk_sys/2
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.scandoubler_disable(scandoubler_disable), // disable scandoubler option from mist.ini
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.no_csync(no_csync), // csync option from mist.ini
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.ypbpr(ypbpr), // YPbPr option from mist.ini
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.rotate(2'b00), // no ODS rotation
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.blend(0), // composite-like blending
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// video input signals to mist_video
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.R (tms_R ),
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.G (tms_G ),
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.B (tms_B ),
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.HSync(tms_HS),
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.VSync(tms_vs),
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// video output signals that go into MiST hardware
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.VGA_R(tms_out_R),
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.VGA_G(tms_out_G),
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.VGA_B(tms_out_B),
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.VGA_VS(tms_out_VS),
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.VGA_HS(tms_out_HS)
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @user_io ***************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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user_io
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#(
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.STRLEN(conf_str_len)
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//.PS2DIV(14) // ps2 clock divider: CLOCK / 14 must be approx = 15 Khz
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)
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user_io (
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.conf_str (CONF_STR ),
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.clk_sys (sys_clock ),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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.SPI_MISO (SPI_DO ),
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.SPI_MOSI (SPI_DI ),
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.status (status ),
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.buttons (buttons ),
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.switches (switches ),
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.scandoubler_disable ( scandoubler_disable ), // get this option from mist.ini
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.ypbpr ( ypbpr ), // get this option from mist.ini
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.no_csync ( no_csync ), // get this option from mist.ini
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.ps2_kbd_clk (ps2_kbd_clk ), // ps2 keyboard from mist firmware
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.ps2_kbd_data (ps2_kbd_data ) // ps2 keyboard from mist firmware
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @sdram *****************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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// SDRAM control signals
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assign SDRAM_CKE = 1'b1;
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/*
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wire [24:0] sdram_addr;
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wire [7:0] sdram_din;
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wire sdram_wr;
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wire sdram_rd;
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wire [7:0] sdram_dout;
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always @(*) begin
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if(is_downloading && download_wr) begin
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sdram_addr <= download_addr;
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sdram_din <= download_data;
|
|
sdram_wr <= download_wr;
|
|
sdram_rd <= 1'b1;
|
|
end
|
|
else if(eraser_busy) begin
|
|
sdram_addr <= eraser_addr;
|
|
sdram_din <= eraser_data;
|
|
sdram_wr <= eraser_wr;
|
|
sdram_rd <= 1'b1;
|
|
end
|
|
else begin
|
|
sdram_addr <= { 9'd0, cpu_addr[15:0] };
|
|
sdram_din <= cpu_dout;
|
|
sdram_wr <= cpu_wr;
|
|
sdram_rd <= cpu_rd;
|
|
end
|
|
end
|
|
*/
|
|
|
|
sdram sdram (
|
|
// interface to the MT48LC16M16 chip
|
|
.sd_data ( SDRAM_DQ ),
|
|
.sd_addr ( SDRAM_A ),
|
|
.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
|
|
.sd_cs ( SDRAM_nCS ),
|
|
.sd_ba ( SDRAM_BA ),
|
|
.sd_we ( SDRAM_nWE ),
|
|
.sd_ras ( SDRAM_nRAS ),
|
|
.sd_cas ( SDRAM_nCAS ),
|
|
|
|
// system interface
|
|
.clk ( sys_clock ),
|
|
.clkref ( cpu_clock ),
|
|
.init ( !pll_locked ),
|
|
|
|
// cpu interface
|
|
.din ( sdram_din ),
|
|
.addr ( sdram_addr ),
|
|
.we ( sdram_wr ),
|
|
.oe ( sdram_rd ),
|
|
.dout ( sdram_dout )
|
|
);
|
|
|
|
/******************************************************************************************/
|
|
/******************************************************************************************/
|
|
/***************************************** @clock *****************************************/
|
|
/******************************************************************************************/
|
|
/******************************************************************************************/
|
|
|
|
wire pixel_clken; // provides the cpu clock enable signal derived from main clock
|
|
wire cpu_clken; // provides the cpu clock enable signal derived from main clock, ram refresh accounted
|
|
wire cpu_clken_noRF; // provides the cpu clock enable signal derived from main clock, without accounting for refresh cycles
|
|
wire cpu_clock; // cpu clock for the sdram controller sync
|
|
|
|
clock clock(
|
|
.sys_clock ( sys_clock ), // input: main clock
|
|
.reset ( reset_button ), // input: reset signal
|
|
|
|
.cpu_clock ( cpu_clock ),
|
|
.cpu_clken ( cpu_clken ), // output: cpu clock enable (phi2)
|
|
.cpu_clken_noRF ( cpu_clken_noRF ), // output: cpu clock enable (phi0)
|
|
.pixel_clken ( pixel_clken ) // output: pixel clock enable
|
|
);
|
|
|
|
/******************************************************************************************/
|
|
/******************************************************************************************/
|
|
/***************************************** @vdp *******************************************/
|
|
/******************************************************************************************/
|
|
/******************************************************************************************/
|
|
|
|
wire vram_we;
|
|
wire [0:13] vram_a;
|
|
wire [0:7] vram_din;
|
|
wire [0:7] vram_dout;
|
|
|
|
vram vram
|
|
(
|
|
.clock ( vdp_clock ),
|
|
.address( vram_a ),
|
|
.data ( vram_din ),
|
|
.wren ( vram_we ),
|
|
.q ( vram_dout )
|
|
);
|
|
|
|
wire [7:0] vdp_dout;
|
|
wire VDP_INT_n;
|
|
|
|
// divide by two the vdp_clock (which is doubled for the scandoubler)
|
|
reg vdp_ena;
|
|
always @(posedge vdp_clock) begin
|
|
vdp_ena <= ~vdp_ena;
|
|
end
|
|
|
|
wire csr = tms_cs & sdram_rd;
|
|
wire csw = tms_cs & sdram_wr;
|
|
|
|
wire tms_HS;
|
|
wire tms_VS;
|
|
wire [5:0] tms_R;
|
|
wire [5:0] tms_G;
|
|
wire [5:0] tms_B;
|
|
|
|
tms9918_async
|
|
#(
|
|
.HORIZONTAL_SHIFT(-36) // -36 good empiric value to center the image on the screen
|
|
)
|
|
tms9918
|
|
(
|
|
// clock
|
|
.RESET(reset_button),
|
|
|
|
.clk(vdp_clock),
|
|
.ena(vdp_ena),
|
|
|
|
/*
|
|
.clk(sys_clock),
|
|
.ena(pixel_clken),
|
|
*/
|
|
|
|
// control signals
|
|
.csr_n ( ~csr ),
|
|
.csw_n ( ~csw ),
|
|
.mode ( sdram_addr[0] ),
|
|
.int_n ( VDP_INT_n ),
|
|
|
|
// cpu I/O
|
|
.cd_i ( sdram_din ),
|
|
.cd_o ( vdp_dout ),
|
|
|
|
// vram
|
|
.vram_we ( vram_we ),
|
|
.vram_a ( vram_a ),
|
|
.vram_d_o ( vram_din ),
|
|
.vram_d_i ( vram_dout ),
|
|
|
|
// video
|
|
.HS(tms_HS),
|
|
.VS(tms_VS),
|
|
.R (tms_R),
|
|
.G (tms_G),
|
|
.B (tms_B)
|
|
);
|
|
|
|
endmodule
|
|
|