53 lines
1.5 KiB
Verilog
53 lines
1.5 KiB
Verilog
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module clock
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(
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input sys_clock, // master clock at cpu x 7 x 8
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input reset, // reset
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output pixel_clken, // 7MHz clock enable for the display
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output cpu_clken, // 1MHz clock enable for the CPU, ram refresh cycles inlcuded
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output cpu_clken_noRF, // 1MHz clock (pure, without refresh cycles)
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output cpu_clock
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);
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localparam CPU_DIVISOR = 56; // (sys_clock / CPU_DIVISOR) = 1 MHz
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localparam PIXEL_DIVISOR = 8; // (sys_clock / PIXEL_DIVISOR) = 7 MHz
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localparam REFRESH_DIVISOR = 65; // counts 65 clock ticks (one complete scanline at phi0 speed)
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reg [5:0] counter_cpu;
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reg [2:0] counter_pixel;
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reg [7:0] counter_refresh;
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always @(posedge sys_clock or posedge reset)
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begin
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if(reset) begin
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counter_cpu <= 0;
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counter_pixel <= 0;
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counter_refresh <= 0;
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end
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else begin
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if (counter_cpu == (CPU_DIVISOR-1)) begin
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counter_cpu <= 0;
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counter_refresh <= (counter_refresh == REFRESH_DIVISOR-1) ? 0 : counter_refresh + 1;
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end
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else
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counter_cpu <= counter_cpu + 1;
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counter_pixel <= (counter_pixel == PIXEL_DIVISOR-1) ? 0 : counter_pixel + 1;
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end
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end
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// the ram refresh cycle is activated by the horizontal counter on every 10 character
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wire RF = counter_refresh == 25 || counter_refresh == 35 || counter_refresh == 45 || counter_refresh == 55;
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assign cpu_clken = counter_cpu == 0 && !RF;
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assign cpu_clken_noRF = counter_cpu == 0;
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assign pixel_clken = counter_pixel == 0;
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assign cpu_clock = counter_pixel < 4 ? 1 : 0;
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endmodule
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