117 lines
2.5 KiB
Verilog
117 lines
2.5 KiB
Verilog
module tms9918
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(
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input RESET,
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input clk,
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input ena,
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// control signals
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input csr_n,
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input csw_n,
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input mode,
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output int_n,
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// cpu I/O
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input [0:7] cd_i,
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output [0:7] cd_o,
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// vram
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output vram_we,
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output [0:13] vram_a,
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output [0:7] vram_d_o,
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input [0:7] vram_d_i,
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// video
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output HS,
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output VS,
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output [5:0] R,
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output [5:0] G,
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output [5:0] B
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);
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vdp18_core
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#(
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.is_pal_g(0) // NTSC
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)
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vdp
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(
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.clk_i ( clk ),
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.clk_en_10m7_i ( ena ),
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.reset_n_i ( ~RESET ),
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.csr_n_i ( csr_n ),
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.csw_n_i ( csw_n ),
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.mode_i ( mode ),
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.int_n_o ( int_n ),
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.cd_i ( cd_i ),
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.cd_o ( cd_o ),
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.vram_we_o ( vram_we ),
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.vram_a_o ( vram_a ),
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.vram_d_o ( vram_d_o ),
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.vram_d_i ( vram_d_i ),
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.rgb_r_o ( vdp_r_ ),
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.rgb_g_o ( vdp_g_ ),
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.rgb_b_o ( vdp_b_ ),
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.hsync_n_o ( vdp_hs ),
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.vsync_n_o ( vdp_vs )
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);
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// video wires
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wire vdp_vs;
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wire vdp_hs;
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wire [0:7] vdp_r_;
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wire [0:7] vdp_g_;
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wire [0:7] vdp_b_;
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wire [5:0] vdp_r = { vdp_r_[0],vdp_r_[1],vdp_r_[2],vdp_r_[3],vdp_r_[4],vdp_r_[5] } ;
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wire [5:0] vdp_g = { vdp_g_[0],vdp_g_[1],vdp_g_[2],vdp_g_[3],vdp_g_[4],vdp_g_[5] } ;
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wire [5:0] vdp_b = { vdp_b_[0],vdp_b_[1],vdp_b_[2],vdp_b_[3],vdp_b_[4],vdp_b_[5] } ;
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @test ******************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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reg [15:0] hcnt;
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reg [15:0] vcnt;
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reg flip = 0;
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localparam EXTRA_PIXELS = 0; // 5
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always @(posedge clk) begin
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if(ena) begin
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if(RESET) begin
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hcnt <= -36;
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vcnt <= 0;
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end
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else begin
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flip = ~flip;
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if(flip) begin
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hcnt <= hcnt + 1;
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if(hcnt == 341+EXTRA_PIXELS) begin
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hcnt <= 0;
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vcnt <= vcnt + 1;
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if(vcnt == 260) vcnt <= 0;
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end
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end
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end
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end
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end
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assign VS = 1 ? (vcnt < 4 ? 0 : 1) : vdp_hs;
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assign HS = 1 ? (hcnt < 20 ? 0 : 1) : vdp_vs;
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wire blank = (vcnt < 8) || (hcnt < 60 || hcnt > 340);
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assign R = 1 ? (blank ? 0 : vdp_r) : vdp_r;
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assign G = 1 ? (blank ? 0 : vdp_g) : vdp_r;
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assign B = 1 ? (blank ? 0 : vdp_b) : vdp_r;
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endmodule
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