202 lines
5.2 KiB
Plaintext
202 lines
5.2 KiB
Plaintext
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A Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A
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==========================================================
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Version: $Date: 2006/06/18 19:28:06 $
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Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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See the file COPYING.
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Integration
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-----------
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The vdp18 design exhibits a set of interface signals that is compatible to the
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original chips. It mainly differs in the video and VRAM interfaces, which are
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tailored to better fit a modern SoC.
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generic (
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is_pal_g : integer := 0;
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-- Select PAL or NTSC video timing.
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-- 0 = NTSC
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-- 1 = PAL
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compat_rgb_g : integer := 0
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-- Select full or compatibility RGB palettes.
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-- Refer to vdp18_col_pack-p.vhd for details.
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);
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port (
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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-- Global clock input
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-- Equivalent to XTAL1/2 on TMS9918A.
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-- Drive with the target frequency of 10.7 MHz or any integer multiple.
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clk_en_10m7_i : in std_logic;
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-- Clock enable
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-- A '1' on this input qualifies a valid rising edge on clk_i. A '0'
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-- disables the next rising clock edge, effectivley halting the design
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-- until the next enabled rising clock edge.
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-- Can be used to run the core at lower frequencies than applied on
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-- clk_i.
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reset_n_i : in std_logic;
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-- Asynchronous low active reset input
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-- Sets all sequential elements to a known state.
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-- NOTE: SYNC operation not supported.
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-- CPU Interface ----------------------------------------------------------
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csr_n_i : in std_logic;
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-- CPU-VDP read strobe, low active
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csw_n_i : in std_logic;
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-- CPU-VDP write strobe, low active
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mode_i : in std_logic;
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-- CPU interface mode select
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int_n_o : out std_logic;
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-- CPU interrupt output, low active
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cd_i : in std_logic_vector(0 to 7);
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-- CPU data bus input
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-- MSB 0 ... 7 LSB
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cd_o : out std_logic_vector(0 to 7);
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-- CPU data bus output
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-- MSB 0 ... 7 LSB
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-- VRAM Interface ---------------------------------------------------------
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vram_we_o : out std_logic;
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-- VRAM write enable
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vram_a_o : out std_logic_vector(0 to 13);
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-- VRAM address output
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-- MSB 0 ... 13 LSB
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vram_d_o : out std_logic_vector(0 to 7);
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-- VRAM data output
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-- MSB 0 ... 7 LSB
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vram_d_i : in std_logic_vector(0 to 7);
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-- VRAM data input
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-- MSB 0 ... 7 LSB
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-- Video Interface --------------------------------------------------------
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col_o : out std_logic_vector(0 to 3);
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-- Color code output
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-- Encoded pixel color information
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rgb_r_o : out std_logic_vector(0 to 7);
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-- Red color information
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rgb_g_o : out std_logic_vector(0 to 7);
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-- Green color information
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rgb_b_o : out std_logic_vector(0 to 7);
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-- Blue color information
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hsync_n_o : out std_logic;
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-- Horizontal synchronization pulse, active low
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vsync_n_o : out std_logic;
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-- Vertical synchronization pulse, active low
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comp_sync_n_o : out std_logic
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-- Composite synchronization pulse, active low
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);
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All 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the MSB
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and bit 7 to be the LSB. This has been implemented according to TI's data
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sheet, thus all register/data format figures apply 1:1 for this design.
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Many systems will flip the system data bus bit wise before it is connected to
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this PSG. This is simply achieved with the following VHDL construct:
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signal data_s : std_logic_vector(7 downto 0);
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...
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cd_i => data_s,
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...
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d_i and data_s will be assigned from left to right, resulting in the expected
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bit assignment:
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cd_i data_s
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0 7
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1 6
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...
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6 1
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7 0
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As this design is fully synchronous, care has to be taken when the design
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replaces an TMS99x8 in asynchronous mode. No problems are expected when
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interfacing the code to other synchronous components.
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Design Hierarchy
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----------------
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vdp18_core
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+-- vdp18_clk_gen
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+-- vdp18_hor_vert
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+-- vdp18_ctrl
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+-- vdp18_cpuio
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+-- vdp18_addr_mux
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+-- vdp18_pattern
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+-- vdp18_sprite
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\-- vdp18_col_mux
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Resulting compolation sequence:
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vdp18_pack-p.vhd
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vdp18_comp_pack-p.vhd
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vdp18_core.vhd
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vdp18_clk_gen.vhd
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vdp18_clk_gen-c.vhd
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vdp18_hor_vert.vhd
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vdp18_hor_vert-c.vhd
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vdp18_ctrl.vhd
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vdp18_ctrl-c.vhd
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vdp18_cpuio.vhd
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vdp18_cpuio-c.vhd
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vdp18_addr_mux.vhd
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vdp18_addr_mux-c.vhd
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vdp18_pattern.vhd
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vdp18_pattern-c.vhd
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vdp18_sprite.vhd
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vdp18_sprite-c.vhd
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vdp18_col_mux.vhd
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vdp18_col_mux-c.vhd
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vdp18_core-c.vhd
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vdp18_core_com_pack-p.vhd
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Skip the files containing VHDL configurations when analyzing the code for
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synthesis.
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References
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----------
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* TI Data book TMS9918.pdf
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http://www.bitsavers.org/pdf/ti/_dataBooks/TMS9918.pdf
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* Sean Young's tech article:
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http://bifi.msxnet.org/msxnet/tech/tms9918a.txt
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* Paul Urbanus' discussion of the timing details
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http://bifi.msxnet.org/msxnet/tech/tmsposting.txt
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* Richard F. Drushel's article series
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"This Week With My Coleco ADAM"
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http://junior.apk.net/~drushel/pub/coleco/twwmca/index.html
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