229 lines
8.2 KiB
VHDL
229 lines
8.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
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--
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-- $Id: vdp18_addr_mux.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $
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--
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-- Address Multiplexer / Generator
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.vdp18_pack.access_t;
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use work.vdp18_pack.opmode_t;
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use work.vdp18_pack.hv_t;
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entity vdp18_addr_mux is
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port (
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access_type_i : in access_t;
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opmode_i : in opmode_t;
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num_line_i : in hv_t;
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reg_ntb_i : in std_logic_vector(0 to 3);
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reg_ctb_i : in std_logic_vector(0 to 7);
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reg_pgb_i : in std_logic_vector(0 to 2);
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reg_satb_i : in std_logic_vector(0 to 6);
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reg_spgb_i : in std_logic_vector(0 to 2);
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reg_size1_i : in boolean;
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cpu_vram_a_i : in std_logic_vector(0 to 13);
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pat_table_i : in std_logic_vector(0 to 9);
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pat_name_i : in std_logic_vector(0 to 7);
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spr_num_i : in std_logic_vector(0 to 4);
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spr_line_i : in std_logic_vector(0 to 3);
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spr_name_i : in std_logic_vector(0 to 7);
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vram_a_o : out std_logic_vector(0 to 13)
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);
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end vdp18_addr_mux;
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use work.vdp18_pack.all;
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architecture rtl of vdp18_addr_mux is
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begin
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-----------------------------------------------------------------------------
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-- Process mux
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--
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-- Purpose:
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-- Generates the VRAM address based on the current access type.
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--
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mux: process (access_type_i, opmode_i,
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num_line_i,
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reg_ntb_i, reg_ctb_i, reg_pgb_i,
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reg_satb_i, reg_spgb_i,
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reg_size1_i,
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cpu_vram_a_i,
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pat_table_i, pat_name_i,
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spr_num_i, spr_name_i,
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spr_line_i)
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variable num_line_v : std_logic_vector(num_line_i'range);
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begin
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-- default assignment
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vram_a_o <= (others => '0');
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num_line_v := std_logic_vector(num_line_i);
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case access_type_i is
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-- CPU Access -----------------------------------------------------------
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when AC_CPU =>
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vram_a_o <= cpu_vram_a_i;
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-- Pattern Name Table Access --------------------------------------------
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when AC_PNT =>
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vram_a_o(0 to 3) <= reg_ntb_i;
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vram_a_o(4 to 13) <= pat_table_i;
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-- Pattern Color Table Access -------------------------------------------
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when AC_PCT =>
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case opmode_i is
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when OPMODE_GRAPH1 =>
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vram_a_o( 0 to 7) <= reg_ctb_i;
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vram_a_o( 8) <= '0';
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vram_a_o( 9 to 13) <= pat_name_i(0 to 4);
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when OPMODE_GRAPH2 =>
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vram_a_o( 0) <= reg_ctb_i(0);
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vram_a_o( 1 to 2) <= num_line_v(1 to 2) and
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-- remaining bits in CTB mask color
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-- lookups
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(reg_ctb_i(1) & reg_ctb_i(2));
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vram_a_o( 3 to 10) <= pat_name_i and
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-- remaining bits in CTB mask color
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-- lookups
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(reg_ctb_i(3) & reg_ctb_i(4) &
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reg_ctb_i(5) & reg_ctb_i(6) &
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reg_ctb_i(7) & "111");
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vram_a_o(11 to 13) <= num_line_v(6 to 8);
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when others =>
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null;
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end case;
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-- Pattern Generator Table Access ---------------------------------------
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when AC_PGT =>
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case opmode_i is
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when OPMODE_TEXTM |
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OPMODE_GRAPH1 =>
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vram_a_o( 0 to 2) <= reg_pgb_i;
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vram_a_o( 3 to 10) <= pat_name_i;
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vram_a_o(11 to 13) <= num_line_v(6 to 8);
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when OPMODE_MULTIC =>
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vram_a_o( 0 to 2) <= reg_pgb_i;
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vram_a_o( 3 to 10) <= pat_name_i;
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vram_a_o(11 to 13) <= num_line_v(4 to 6);
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when OPMODE_GRAPH2 =>
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vram_a_o( 0) <= reg_pgb_i(0);
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vram_a_o( 1 to 2) <= num_line_v(1 to 2) and
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-- remaining bits in PGB mask pattern
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-- lookups
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(reg_pgb_i(1) & reg_pgb_i(2));
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vram_a_o( 3 to 10) <= pat_name_i and
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-- remaining bits in CTB mask pattern
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-- lookups
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(reg_ctb_i(3) & reg_ctb_i(4) &
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reg_ctb_i(5) & reg_ctb_i(6) &
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reg_ctb_i(7) & "111");
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vram_a_o(11 to 13) <= num_line_v(6 to 8);
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when others =>
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null;
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end case;
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-- Sprite Test ----------------------------------------------------------
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when AC_STST |
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AC_SATY =>
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vram_a_o( 0 to 6) <= reg_satb_i;
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vram_a_o( 7 to 11) <= spr_num_i;
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vram_a_o(12 to 13) <= "00";
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-- Sprite Attribute Table: X --------------------------------------------
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when AC_SATX =>
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vram_a_o( 0 to 6) <= reg_satb_i;
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vram_a_o( 7 to 11) <= spr_num_i;
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vram_a_o(12 to 13) <= "01";
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-- Sprite Attribute Table: Name -----------------------------------------
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when AC_SATN =>
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vram_a_o( 0 to 6) <= reg_satb_i;
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vram_a_o( 7 to 11) <= spr_num_i;
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vram_a_o(12 to 13) <= "10";
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-- Sprite Attribute Table: Color ----------------------------------------
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when AC_SATC =>
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vram_a_o( 0 to 6) <= reg_satb_i;
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vram_a_o( 7 to 11) <= spr_num_i;
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vram_a_o(12 to 13) <= "11";
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-- Sprite Pattern, Upper Part -------------------------------------------
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when AC_SPTH =>
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vram_a_o( 0 to 2) <= reg_spgb_i;
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if not reg_size1_i then
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-- 8x8 sprite
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vram_a_o( 3 to 10) <= spr_name_i;
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vram_a_o(11 to 13) <= spr_line_i(1 to 3);
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else
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-- 16x16 sprite
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vram_a_o( 3 to 8) <= spr_name_i(0 to 5);
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vram_a_o( 9) <= '0';
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vram_a_o(10 to 13) <= spr_line_i;
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end if;
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-- Sprite Pattern, Lower Part -------------------------------------------
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when AC_SPTL =>
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vram_a_o( 0 to 2) <= reg_spgb_i;
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vram_a_o( 3 to 8) <= spr_name_i(0 to 5);
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vram_a_o( 9) <= '1';
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vram_a_o(10 to 13) <= spr_line_i;
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when others =>
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null;
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end case;
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end process mux;
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--
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-----------------------------------------------------------------------------
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end rtl;
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