155 lines
4.6 KiB
VHDL
155 lines
4.6 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
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--
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-- $Id: vdp18_clk_gen.vhd,v 1.8 2006/06/18 10:47:01 arnim Exp $
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--
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-- Clock Generator
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity vdp18_clk_gen is
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port (
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clk_i : in std_logic;
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clk_en_10m7_i : in std_logic;
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reset_i : in boolean;
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clk_en_5m37_o : out boolean;
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clk_en_3m58_o : out boolean;
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clk_en_2m68_o : out boolean
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);
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end vdp18_clk_gen;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of vdp18_clk_gen is
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signal cnt_q : unsigned(3 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the sequential elements.
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-- * clock counter
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--
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seq: process (clk_i, reset_i)
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variable cnt_v : integer range -256 to 255;
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begin
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if reset_i then
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cnt_q <= (others => '0');
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elsif clk_i'event and clk_i = '1' then
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if clk_en_10m7_i = '1' then
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if cnt_q = 11 then
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-- wrap after counting 12 clocks
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cnt_q <= (others => '0');
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else
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cnt_q <= cnt_q + 1;
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end if;
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end if;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process clk_en
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--
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-- Purpose:
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-- Generates the derived clock enable signals.
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--
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clk_en: process (clk_en_10m7_i,
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cnt_q)
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variable cnt_v : integer range -256 to 255;
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begin
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cnt_v := to_integer(cnt_q);
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-- 5.37 MHz clock enable --------------------------------------------------
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if clk_en_10m7_i = '1' then
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case cnt_v is
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when 1 | 3 | 5 | 7 | 9 | 11 =>
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clk_en_5m37_o <= true;
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when others =>
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clk_en_5m37_o <= false;
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end case;
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else
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clk_en_5m37_o <= false;
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end if;
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-- 3.58 MHz clock enable --------------------------------------------------
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if clk_en_10m7_i = '1' then
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case cnt_v is
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when 2 | 5 | 8 | 11 =>
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clk_en_3m58_o <= true;
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when others =>
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clk_en_3m58_o <= false;
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end case;
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else
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clk_en_3m58_o <= false;
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end if;
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-- 2.68 MHz clock enable --------------------------------------------------
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if clk_en_10m7_i = '1' then
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case cnt_v is
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when 3 | 7 | 11 =>
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clk_en_2m68_o <= true;
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when others =>
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clk_en_2m68_o <= false;
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end case;
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else
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clk_en_2m68_o <= false;
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end if;
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end process clk_en;
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--
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-----------------------------------------------------------------------------
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end rtl;
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