185 lines
6.0 KiB
VHDL
185 lines
6.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
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--
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-- $Id: vdp18_col_mux.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $
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--
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-- Color Information Multiplexer
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity vdp18_col_mux is
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generic (
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compat_rgb_g : integer := 0
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);
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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reset_i : in boolean;
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vert_active_i : in boolean;
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hor_active_i : in boolean;
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blank_i : in boolean;
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reg_col0_i : in std_logic_vector(0 to 3);
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pat_col_i : in std_logic_vector(0 to 3);
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spr0_col_i : in std_logic_vector(0 to 3);
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spr1_col_i : in std_logic_vector(0 to 3);
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spr2_col_i : in std_logic_vector(0 to 3);
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spr3_col_i : in std_logic_vector(0 to 3);
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col_o : out std_logic_vector(0 to 3);
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rgb_r_o : out std_logic_vector(0 to 7);
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rgb_g_o : out std_logic_vector(0 to 7);
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rgb_b_o : out std_logic_vector(0 to 7)
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);
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end vdp18_col_mux;
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library ieee;
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use ieee.numeric_std.all;
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use work.vdp18_col_pack.all;
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architecture rtl of vdp18_col_mux is
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signal col_s : std_logic_vector(0 to 3);
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begin
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-----------------------------------------------------------------------------
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-- Process col_mux
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--
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-- Purpose:
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-- Multiplexes the color information from different sources.
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--
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col_mux: process (blank_i,
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hor_active_i, vert_active_i,
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spr0_col_i, spr1_col_i,
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spr2_col_i, spr3_col_i,
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pat_col_i,
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reg_col0_i)
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begin
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if not blank_i then
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if hor_active_i and vert_active_i then
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-- priority decoder
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if spr0_col_i /= "0000" then
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col_s <= spr0_col_i;
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elsif spr1_col_i /= "0000" then
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col_s <= spr1_col_i;
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elsif spr2_col_i /= "0000" then
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col_s <= spr2_col_i;
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elsif spr3_col_i /= "0000" then
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col_s <= spr3_col_i;
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elsif pat_col_i /= "0000" then
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col_s <= pat_col_i;
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else
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col_s <= reg_col0_i;
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end if;
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else
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-- display border
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col_s <= reg_col0_i;
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end if;
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else
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-- blank color channels during horizontal and vertical
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-- trace back
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-- required to initialize colors for each new scan line
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col_s <= (others => '0');
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end if;
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end process col_mux;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process rgb_reg
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--
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-- Purpose:
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-- Converts the color information to simple RGB and saves these in
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-- output registers.
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--
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rgb_reg: process (clk_i, reset_i)
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variable col_v : natural range 0 to 15;
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variable rgb_r_v,
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rgb_g_v,
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rgb_b_v : rgb_val_t;
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variable rgb_table_v : rgb_table_t;
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begin
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if reset_i then
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rgb_r_o <= (others => '0');
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rgb_g_o <= (others => '0');
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rgb_b_o <= (others => '0');
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elsif clk_i'event and clk_i = '1' then
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if clk_en_5m37_i then
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-- select requested RGB table
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if compat_rgb_g = 1 then
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rgb_table_v := compat_rgb_table_c;
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else
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rgb_table_v := full_rgb_table_c;
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end if;
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-- assign color to RGB channels
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col_v := to_integer(unsigned(col_s));
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rgb_r_v := rgb_table_v(col_v)(r_c);
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rgb_g_v := rgb_table_v(col_v)(g_c);
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rgb_b_v := rgb_table_v(col_v)(b_c);
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--
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rgb_r_o <= std_logic_vector(to_unsigned(rgb_r_v, 8));
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rgb_g_o <= std_logic_vector(to_unsigned(rgb_g_v, 8));
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rgb_b_o <= std_logic_vector(to_unsigned(rgb_b_v, 8));
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end if;
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end if;
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end process rgb_reg;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-----------------------------------------------------------------------------
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col_o <= col_s;
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end rtl;
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