200 lines
6.5 KiB
VHDL
200 lines
6.5 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- $Id: vdp18_comp_pack-p.vhd,v 1.23 2006/02/28 22:30:41 arnim Exp $
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.vdp18_pack.opmode_t;
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use work.vdp18_pack.hv_t;
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use work.vdp18_pack.access_t;
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package vdp18_comp_pack is
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component vdp18_clk_gen
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port (
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clk_i : in std_logic;
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clk_en_10m7_i : in std_logic;
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reset_i : in boolean;
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clk_en_5m37_o : out boolean;
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clk_en_3m58_o : out boolean;
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clk_en_2m68_o : out boolean
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);
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end component;
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component vdp18_hor_vert
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generic (
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is_pal_g : integer := 0
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);
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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reset_i : in boolean;
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opmode_i : in opmode_t;
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num_pix_o : out hv_t;
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num_line_o : out hv_t;
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vert_inc_o : out boolean;
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hsync_n_o : out std_logic;
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vsync_n_o : out std_logic;
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blank_o : out boolean
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);
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end component;
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component vdp18_ctrl
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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reset_i : in boolean;
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opmode_i : in opmode_t;
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num_pix_i : in hv_t;
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num_line_i : in hv_t;
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vert_inc_i : in boolean;
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reg_blank_i : in boolean;
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reg_size1_i : in boolean;
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stop_sprite_i : in boolean;
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clk_en_acc_o : out boolean;
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access_type_o : out access_t;
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vert_active_o : out boolean;
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hor_active_o : out boolean;
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irq_o : out boolean
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);
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end component;
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component vdp18_cpuio
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port (
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clk_i : in std_logic;
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clk_en_10m7_i : in boolean;
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clk_en_acc_i : in boolean;
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reset_i : in boolean;
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rd_i : in boolean;
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wr_i : in boolean;
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mode_i : in std_logic;
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cd_i : in std_logic_vector(0 to 7);
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cd_o : out std_logic_vector(0 to 7);
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cd_oe_o : out std_logic;
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access_type_i : in access_t;
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opmode_o : out opmode_t;
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vram_we_o : out std_logic;
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vram_a_o : out std_logic_vector(0 to 13);
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vram_d_o : out std_logic_vector(0 to 7);
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vram_d_i : in std_logic_vector(0 to 7);
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spr_coll_i : in boolean;
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spr_5th_i : in boolean;
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spr_5th_num_i : in std_logic_vector(0 to 4);
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reg_ev_o : out boolean;
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reg_16k_o : out boolean;
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reg_blank_o : out boolean;
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reg_size1_o : out boolean;
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reg_mag1_o : out boolean;
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reg_ntb_o : out std_logic_vector(0 to 3);
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reg_ctb_o : out std_logic_vector(0 to 7);
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reg_pgb_o : out std_logic_vector(0 to 2);
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reg_satb_o : out std_logic_vector(0 to 6);
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reg_spgb_o : out std_logic_vector(0 to 2);
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reg_col1_o : out std_logic_vector(0 to 3);
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reg_col0_o : out std_logic_vector(0 to 3);
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irq_i : in boolean;
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int_n_o : out std_logic
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);
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end component;
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component vdp18_addr_mux
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port (
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access_type_i : in access_t;
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opmode_i : in opmode_t;
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num_line_i : in hv_t;
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reg_ntb_i : in std_logic_vector(0 to 3);
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reg_ctb_i : in std_logic_vector(0 to 7);
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reg_pgb_i : in std_logic_vector(0 to 2);
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reg_satb_i : in std_logic_vector(0 to 6);
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reg_spgb_i : in std_logic_vector(0 to 2);
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reg_size1_i : in boolean;
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cpu_vram_a_i : in std_logic_vector(0 to 13);
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pat_table_i : in std_logic_vector(0 to 9);
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pat_name_i : in std_logic_vector(0 to 7);
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spr_num_i : in std_logic_vector(0 to 4);
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spr_line_i : in std_logic_vector(0 to 3);
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spr_name_i : in std_logic_vector(0 to 7);
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vram_a_o : out std_logic_vector(0 to 13)
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);
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end component;
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component vdp18_pattern
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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clk_en_acc_i : in boolean;
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reset_i : in boolean;
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opmode_i : in opmode_t;
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access_type_i : in access_t;
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num_line_i : in hv_t;
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vram_d_i : in std_logic_vector(0 to 7);
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vert_inc_i : in boolean;
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vsync_n_i : in std_logic;
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reg_col1_i : in std_logic_vector(0 to 3);
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reg_col0_i : in std_logic_vector(0 to 3);
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pat_table_o : out std_logic_vector(0 to 9);
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pat_name_o : out std_logic_vector(0 to 7);
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pat_col_o : out std_logic_vector(0 to 3)
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);
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end component;
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component vdp18_sprite
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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clk_en_acc_i : in boolean;
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reset_i : in boolean;
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access_type_i : in access_t;
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num_pix_i : in hv_t;
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num_line_i : in hv_t;
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vram_d_i : in std_logic_vector(0 to 7);
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vert_inc_i : in boolean;
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reg_size1_i : in boolean;
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reg_mag1_i : in boolean;
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spr_5th_o : out boolean;
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spr_5th_num_o : out std_logic_vector(0 to 4);
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stop_sprite_o : out boolean;
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spr_coll_o : out boolean;
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spr_num_o : out std_logic_vector(0 to 4);
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spr_line_o : out std_logic_vector(0 to 3);
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spr_name_o : out std_logic_vector(0 to 7);
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spr0_col_o : out std_logic_vector(0 to 3);
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spr1_col_o : out std_logic_vector(0 to 3);
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spr2_col_o : out std_logic_vector(0 to 3);
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spr3_col_o : out std_logic_vector(0 to 3)
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);
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end component;
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component vdp18_col_mux
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generic (
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compat_rgb_g : integer := 0
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);
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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reset_i : in boolean;
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vert_active_i : in boolean;
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hor_active_i : in boolean;
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blank_i : in boolean;
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reg_col0_i : in std_logic_vector(0 to 3);
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pat_col_i : in std_logic_vector(0 to 3);
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spr0_col_i : in std_logic_vector(0 to 3);
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spr1_col_i : in std_logic_vector(0 to 3);
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spr2_col_i : in std_logic_vector(0 to 3);
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spr3_col_i : in std_logic_vector(0 to 3);
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col_o : out std_logic_vector(0 to 3);
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rgb_r_o : out std_logic_vector(0 to 7);
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rgb_g_o : out std_logic_vector(0 to 7);
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rgb_b_o : out std_logic_vector(0 to 7)
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);
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end component;
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end vdp18_comp_pack;
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