48 lines
1.1 KiB
VHDL
48 lines
1.1 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
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--
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-- $Id: vdp18_core-c.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $
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--
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-------------------------------------------------------------------------------
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configuration vdp18_core_struct_c0 of vdp18_core is
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for struct
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for clk_gen_b: vdp18_clk_gen
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use configuration work.vdp18_clk_gen_rtl_c0;
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end for;
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for hor_vert_b: vdp18_hor_vert
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use configuration work.vdp18_hor_vert_rtl_c0;
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end for;
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for ctrl_b: vdp18_ctrl
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use configuration work.vdp18_ctrl_rtl_c0;
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end for;
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for cpu_io_b: vdp18_cpuio
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use configuration work.vdp18_cpuio_rtl_c0;
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end for;
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for addr_mux_b: vdp18_addr_mux
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use configuration work.vdp18_addr_mux_rtl_c0;
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end for;
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for pattern_b: vdp18_pattern
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use configuration work.vdp18_pattern_rtl_c0;
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end for;
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for sprite_b: vdp18_sprite
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use configuration work.vdp18_sprite_rtl_c0;
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end for;
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for col_mux_b: vdp18_col_mux
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use configuration work.vdp18_col_mux_rtl_c0;
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end for;
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end for;
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end vdp18_core_struct_c0;
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