282 lines
8.2 KiB
VHDL
282 lines
8.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- $Id: vdp18_pack-p.vhd,v 1.14 2006/02/22 23:07:05 arnim Exp $
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package vdp18_pack is
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-----------------------------------------------------------------------------
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-- Subtype for horizontal/vertical counters/positions.
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--
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subtype hv_t is signed(0 to 8);
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Constants for first and last vertical line of NTSC and PAL mode.
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--
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constant hv_first_line_ntsc_c : hv_t := to_signed(-40, hv_t'length);
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constant hv_last_line_ntsc_c : hv_t := to_signed(221, hv_t'length);
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--
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constant hv_first_line_pal_c : hv_t := to_signed(-65, hv_t'length);
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constant hv_last_line_pal_c : hv_t := to_signed(247, hv_t'length);
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Constants for first and last horizontal pixel in text and graphics.
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--
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constant hv_first_pix_text_c : hv_t := to_signed(-102, hv_t'length);
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constant hv_last_pix_text_c : hv_t := to_signed(239, hv_t'length);
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--
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constant hv_first_pix_graph_c : hv_t := to_signed(-86, hv_t'length);
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constant hv_last_pix_graph_c : hv_t := to_signed(255, hv_t'length);
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Miscellaneous constants for horizontal phases.
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--
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constant hv_vertical_inc_c : hv_t := to_signed(-32, hv_t'length);
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constant hv_sprite_start_c : hv_t := to_signed(247, hv_t'length);
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Operating modes of the VDP18 core.
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--
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type opmode_t is (OPMODE_GRAPH1, OPMODE_GRAPH2,
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OPMODE_MULTIC, OPMODE_TEXTM);
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--
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constant opmode_graph1_c : std_logic_vector(0 to 2) := "000";
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constant opmode_graph2_c : std_logic_vector(0 to 2) := "001";
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constant opmode_multic_c : std_logic_vector(0 to 2) := "010";
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constant opmode_textm_c : std_logic_vector(0 to 2) := "100";
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Access types.
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--
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type access_t is (-- pattern access
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-- read Pattern Name Table
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AC_PNT,
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-- read Pattern Generator Table
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AC_PGT,
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-- read Pattern Color Table
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AC_PCT,
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-- sprite access
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-- sprite test read (y coordinate)
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AC_STST,
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-- read Sprite Attribute Table/Y
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AC_SATY,
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-- read Sprite Attribute Table/X
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AC_SATX,
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-- read Sprite Attribute Table/N
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AC_SATN,
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-- read Sprite Attribute Table/C
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AC_SATC,
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-- read Sprite Pattern Table/high quadrant
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AC_SPTH,
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-- read Sprite Pattern Table/low quadrant
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AC_SPTL,
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--
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-- CPU access
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AC_CPU,
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--
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-- no access at all
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AC_NONE
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);
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function enum_to_vec_f
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--
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-- Purpose:
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-- Translate access_t enumeration type to std_logic_vector.
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--
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function enum_to_vec_f(enum : in access_t) return
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std_logic_vector;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function to_boolean_f
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--
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-- Purpose:
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-- Converts a std_logic value to boolean.
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--
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function to_boolean_f(val : in std_logic) return boolean;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function to_std_logic_f
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--
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-- Purpose:
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-- Converts a boolean value to std_logic.
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--
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function to_std_logic_f(val : in boolean) return std_logic;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function mod_6_f
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--
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-- Purpose:
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-- Calculate the modulo of 6.
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-- Only the positive part is considered.
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--
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function mod_6_f(val : in hv_t) return hv_t;
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--
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-----------------------------------------------------------------------------
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end vdp18_pack;
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package body vdp18_pack is
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-----------------------------------------------------------------------------
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-- Function enum_to_vec_f
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--
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-- Purpose:
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-- Translate access_t enumeration type to std_logic_vector.
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--
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function enum_to_vec_f(enum : in access_t) return
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std_logic_vector is
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variable result_v : std_logic_vector(3 downto 0);
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begin
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case enum is
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when AC_NONE =>
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result_v := "0000";
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when AC_PNT =>
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result_v := "0001";
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when AC_PGT =>
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result_v := "0010";
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when AC_PCT =>
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result_v := "0011";
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when AC_STST =>
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result_v := "0100";
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when AC_SATY =>
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result_v := "0101";
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when AC_SATX =>
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result_v := "0110";
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when AC_SATN =>
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result_v := "0111";
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when AC_SATC =>
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result_v := "1000";
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when AC_SPTL =>
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result_v := "1001";
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when AC_SPTH =>
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result_v := "1010";
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when AC_CPU =>
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result_v := "1111";
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when others =>
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result_v := "UUUU";
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end case;
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return result_v;
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end;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function to_boolean_f
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--
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-- Purpose:
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-- Converts a std_logic value to boolean.
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--
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function to_boolean_f(val : in std_logic) return boolean is
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variable result_v : boolean;
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begin
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case to_X01(val) is
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when '1' =>
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result_v := true;
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when '0' =>
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result_v := false;
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when others =>
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result_v := false;
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end case;
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return result_v;
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end;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function to_std_logic_f
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--
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-- Purpose:
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-- Converts a boolean value to std_logic.
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--
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function to_std_logic_f(val : in boolean) return std_logic is
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variable result_v : std_logic;
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begin
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case val is
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when true =>
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result_v := '1';
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when false =>
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result_v := '0';
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end case;
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return result_v;
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end;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Function mod_6_f
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--
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-- Purpose:
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-- Calculate the modulo of 6.
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-- Only the positive part is considered.
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--
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function mod_6_f(val : in hv_t) return hv_t is
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variable mod_v : natural;
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variable result_v : hv_t;
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begin
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if val(0) = '0' then
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result_v := (others => '0');
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mod_v := 0;
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for idx in 0 to 255 loop
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if val = idx then
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result_v := to_signed(mod_v, hv_t'length);
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end if;
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if mod_v < 5 then
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mod_v := mod_v + 1;
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else
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mod_v := 0;
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end if;
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end loop;
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else
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result_v := (others => '-');
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end if;
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return result_v;
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end;
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--
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-----------------------------------------------------------------------------
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end vdp18_pack;
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