234 lines
7.2 KiB
VHDL
234 lines
7.2 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
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--
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-- $Id: vdp18_pattern.vhd,v 1.8 2006/06/18 10:47:06 arnim Exp $
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--
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-- Pattern Generation Controller
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.vdp18_pack.opmode_t;
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use work.vdp18_pack.access_t;
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use work.vdp18_pack.hv_t;
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entity vdp18_pattern is
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port (
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clk_i : in std_logic;
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clk_en_5m37_i : in boolean;
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clk_en_acc_i : in boolean;
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reset_i : in boolean;
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opmode_i : in opmode_t;
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access_type_i : in access_t;
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num_line_i : in hv_t;
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vram_d_i : in std_logic_vector(0 to 7);
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vert_inc_i : in boolean;
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vsync_n_i : in std_logic;
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reg_col1_i : in std_logic_vector(0 to 3);
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reg_col0_i : in std_logic_vector(0 to 3);
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pat_table_o : out std_logic_vector(0 to 9);
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pat_name_o : out std_logic_vector(0 to 7);
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pat_col_o : out std_logic_vector(0 to 3)
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);
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end vdp18_pattern;
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library ieee;
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use ieee.numeric_std.all;
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use work.vdp18_pack.all;
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architecture rtl of vdp18_pattern is
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signal pat_cnt_q : unsigned(0 to 9);
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signal pat_name_q,
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pat_tmp_q,
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pat_shift_q,
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pat_col_q : std_logic_vector(0 to 7);
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begin
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the sequential elements:
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-- * pattern shift register
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-- * pattern color register
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-- * pattern counter
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--
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seq: process (clk_i, reset_i)
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begin
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if reset_i then
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pat_cnt_q <= (others => '0');
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pat_name_q <= (others => '0');
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pat_tmp_q <= (others => '0');
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pat_shift_q <= (others => '0');
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pat_col_q <= (others => '0');
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elsif clk_i'event and clk_i = '1' then
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if clk_en_5m37_i then
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-- shift pattern with every pixel clock
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pat_shift_q(0 to 6) <= pat_shift_q(1 to 7);
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end if;
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if clk_en_acc_i then
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-- determine register update based on current access type -------------
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case access_type_i is
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when AC_PNT =>
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-- store pattern name
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pat_name_q <= vram_d_i;
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-- increment pattern counter
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pat_cnt_q <= pat_cnt_q + 1;
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when AC_PCT =>
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-- store pattern color in temporary register
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pat_tmp_q <= vram_d_i;
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when AC_PGT =>
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if opmode_i = OPMODE_MULTIC then
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-- set shift register to constant value
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-- this value generates 4 bits of color1
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-- followed by 4 bits of color0
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pat_shift_q <= "11110000";
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-- set pattern color from pattern generator memory
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pat_col_q <= vram_d_i;
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else
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-- all other modes:
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-- store pattern line in shift register
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pat_shift_q <= vram_d_i;
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-- move pattern color from temporary register to color register
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pat_col_q <= pat_tmp_q;
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end if;
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when others =>
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null;
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end case;
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end if;
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if vert_inc_i then
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-- redo patterns of if there are more lines inside this pattern
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if num_line_i(0) = '0' then
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case opmode_i is
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when OPMODE_TEXTM =>
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if num_line_i(6 to 8) /= "111" then
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pat_cnt_q <= pat_cnt_q - 40;
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end if;
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when OPMODE_GRAPH1 |
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OPMODE_GRAPH2 |
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OPMODE_MULTIC =>
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if num_line_i(6 to 8) /= "111" then
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pat_cnt_q <= pat_cnt_q - 32;
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end if;
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end case;
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end if;
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end if;
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if vsync_n_i = '0' then
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-- reset pattern counter at end of active display area
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pat_cnt_q <= (others => '0');
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end if;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process col_gen
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--
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-- Purpose:
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-- Generates the color of the current pattern pixel.
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--
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col_gen: process (opmode_i,
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pat_shift_q,
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pat_col_q,
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reg_col1_i,
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reg_col0_i)
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variable pix_v : std_logic;
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begin
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-- default assignment
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pat_col_o <= "0000";
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pix_v := pat_shift_q(0);
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case opmode_i is
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-- Text Mode ------------------------------------------------------------
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when OPMODE_TEXTM =>
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if pix_v = '1' then
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pat_col_o <= reg_col1_i;
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else
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pat_col_o <= reg_col0_i;
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end if;
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-- Graphics I, II and Multicolor Mode -----------------------------------
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when OPMODE_GRAPH1 |
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OPMODE_GRAPH2 |
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OPMODE_MULTIC =>
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if pix_v = '1' then
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pat_col_o <= pat_col_q(0 to 3);
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else
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pat_col_o <= pat_col_q(4 to 7);
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end if;
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when others =>
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null;
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end case;
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end process col_gen;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping
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-----------------------------------------------------------------------------
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pat_table_o <= std_logic_vector(pat_cnt_q);
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pat_name_o <= pat_name_q;
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end rtl;
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