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-- 65xx compatible microprocessor core -- -- Copyright (c) 2002...2015 -- Daniel Wallner (jesus <at> opencores <dot> org) -- Mike Johnson (mikej <at> fpgaarcade <dot> com) -- Wolfgang Scherr (WoS <at> pin4 <dot> at> -- Morten Leikvoll () -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author(s), but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- ----- IMPORTANT NOTES ----- -- -- Limitations: -- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes) -- 65C02 supported : inc, dec, phx, plx, phy, ply -- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 -- Some interface signals behave incorrect -- NMI interrupt handling not nice, needs further rework (to cycle-based encoding). -- -- Usage: -- The enable signal allows clock gating / throttling without using the ready signal. -- Set it to constant '1' when using the Clk input as the CPU clock directly. -- -- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0', -- otherwise some undocumented opcodes won't work correctly. -- EXAMPLE: -- CPU : entity work.T65 -- port map ( -- R_W_n => cpu_rwn_s, -- [....all other ports....] -- DI => cpu_din_s, -- DO => cpu_dout_s -- ); -- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else -- [....other sources from peripherals and memories...] -- -- ----- IMPORTANT NOTES ----- --