146 lines
4.3 KiB
Verilog
146 lines
4.3 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple1 hardware core
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module apple1(
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input reset, // reset
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input sys_clock, // system clock
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input pixel_clken, // 7 MHz pixel clock
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input cpu_clken, // cpu clock enable
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// RAM interface
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output [15:0] ram_addr,
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output [7:0] ram_din,
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input [7:0] ram_dout,
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output ram_rd,
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output ram_wr,
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// I/O interface to keyboard
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input ps2_clk, // PS/2 keyboard serial clock input
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input ps2_din, // PS/2 keyboard serial data input
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// interrupt signa
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input INT_n,
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output vga_red, // red VGA signal
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output vga_grn, // green VGA signal
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output vga_blu, // blue VGA signal
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input vga_cls, // clear screen button
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output reset_key, // keyboard shortcut for reset
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output poweroff_key // keyboard shortcut for poweroff/on
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);
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assign ram_addr = addr;
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assign ram_din = cpu_dout;
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assign ram_rd = ram_cs;
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assign ram_wr = we & ram_cs;
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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wire [15:0] addr;
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wire [7:0] cpu_din;
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wire [7:0] cpu_dout;
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wire we;
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//////////////////////////////////////////////////////////////////////////
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// 6502
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arlet_6502 arlet_6502(
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.clk (sys_clock),
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.enable (cpu_clken),
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.rst (reset),
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.ab (addr),
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.dbi (cpu_din),
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.dbo (cpu_dout),
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.we (we),
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.irq_n (INT_n),
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.nmi_n (1'b1),
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.ready (cpu_clken)
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);
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//////////////////////////////////////////////////////////////////////////
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// Address Decoding
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wire keyboard_cs = (addr[15:1] == 15'b110100000001000); // 0xD010 -> 0xD011
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wire display_cs = (addr[15:1] == 15'b110100000001001); // 0xD012 -> 0xD013
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wire ram_cs = !keyboard_cs & !display_cs;
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// byte returned from display out
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wire [7:0] display_dout = { ~PB7, 7'b0 };
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//////////////////////////////////////////////////////////////////////////
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// Peripherals
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// PS/2 keyboard interface
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wire [7:0] ps2_dout;
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wire cls_key;
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ps2keyboard keyboard(
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.clk(sys_clock),
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.rst(reset),
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.key_clk(ps2_clk),
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.key_din(ps2_din),
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.cs(keyboard_cs),
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.address(addr[0]),
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.dout(ps2_dout),
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.cls_key(cls_key),
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.reset_key(reset_key),
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.poweroff_key(poweroff_key)
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);
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wire PB7; // (negated) display ready (PB7 of CIA)
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display display(
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.reset(reset),
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.sys_clock(sys_clock),
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.pixel_clken(pixel_clken),
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.cpu_clken(cpu_clken & display_cs),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.address(addr[0]),
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.w_en(we & display_cs),
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.din(cpu_dout),
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.clr_screen(cls_key),
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.ready(PB7)
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);
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//////////////////////////////////////////////////////////////////////////
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// CPU Data In MUX
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// link up chip selected device to cpu input
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assign cpu_din = display_cs ? display_dout :
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keyboard_cs ? ps2_dout :
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ram_cs ? ram_dout :
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8'hFF;
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endmodule
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