53 lines
1.2 KiB
Verilog
53 lines
1.2 KiB
Verilog
// Apple-1 Audio cassette interface (ACI)
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// A good explanation of ACI can be found at:
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// https://www.sbprojects.net/projects/apple1/aci.php
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module ACI (
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input clk, // clock signal
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input cpu_clken, // CPU clock enable
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input [15:0] addr, // address bus
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output reg [7:0] dout, // 8-bit data bus (output)
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output reg tape_out, // tape output
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input tape_in // tape input
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);
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reg [7:0] rom_data[0:255];
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initial
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$readmemh("roms/aci.hex", rom_data, 0, 255);
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wire io_range = addr >= 16'hC000 && addr <= 16'hC0FF;
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wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & debounced_tape_in } : addr[7:0];
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always @(posedge clk) begin
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if(cpu_clken & io_range)
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tape_out <= ~tape_out;
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dout <= rom_data[read_addr];
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end
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// filters tape_in with anti bounce
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wire debounced_tape_in = last_tape_in;
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reg last_tape_in;
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reg [31:0] bounce_cnt;
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localparam bounce_max = 3579; // 57272719 / 3579 = ~16 KHz max
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always @(posedge clk) begin
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if(tape_in != last_tape_in) begin
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if(bounce_cnt < bounce_max) begin
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bounce_cnt <= bounce_cnt + 1;
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end
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else begin
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bounce_cnt <= 0;
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last_tape_in = tape_in;
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end
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end
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end
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endmodule
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