69 lines
3.1 KiB
Plaintext
69 lines
3.1 KiB
Plaintext
-- 65xx compatible microprocessor core
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--
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-- Copyright (c) 2002...2015
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-- Daniel Wallner (jesus <at> opencores <dot> org)
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-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
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-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
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-- Morten Leikvoll ()
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author(s), but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- ----- IMPORTANT NOTES -----
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--
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-- Limitations:
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-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
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-- 65C02 supported : inc, dec, phx, plx, phy, ply
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-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
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-- Some interface signals behave incorrect
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-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
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--
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-- Usage:
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-- The enable signal allows clock gating / throttling without using the ready signal.
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-- Set it to constant '1' when using the Clk input as the CPU clock directly.
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--
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-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
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-- otherwise some undocumented opcodes won't work correctly.
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-- EXAMPLE:
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-- CPU : entity work.T65
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-- port map (
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-- R_W_n => cpu_rwn_s,
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-- [....all other ports....]
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-- DI => cpu_din_s,
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-- DO => cpu_dout_s
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-- );
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-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
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-- [....other sources from peripherals and memories...]
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--
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-- ----- IMPORTANT NOTES -----
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--
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