287 lines
9.4 KiB
Verilog
287 lines
9.4 KiB
Verilog
module display (
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input reset, // active high reset signal
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input sys_clock, // system clock
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input pixel_clken, // pixel clock enable
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input cpu_clken, // cpu clock enable
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input clr_screen, // clear screen button
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// video output
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output vga_h_sync, // horizontal sync pulse
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output vga_v_sync, // vertical sync pulse
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output [5:0] vga_red, // red signal
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output [5:0] vga_grn, // green signal
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output [5:0] vga_blu, // blue signal
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output reg ready, // display ready (PB7 of CIA)
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// cpu interface
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input address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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output reg [6:0] dout // input data is also seen as output
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Parameters
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// video structure constants
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parameter h_pixels = 455; // 910; // horizontal pixels per line
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parameter h_pulse = 32; // 65; // hsync pulse length
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parameter hbp = 104; // 208; // end of horizontal back porch
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parameter hfp = 424; // 848; // beginning of horizontal front porch
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parameter v_lines = 262; // vertical lines per frame
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parameter v_pulse = 2; // vsync pulse length
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parameter vbp = 42; // end of vertical back porch
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parameter vfp = 234; // beginning of vertical front porch
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// registers for storing the horizontal & vertical counters
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reg [9:0] h_cnt; // horizontal counter
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reg [9:0] v_cnt; // vertical counter
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reg [2:0] v_dot; // vertical counter within character matrix (0-7)
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wire [2:0] h_dot; // horizontal counter within character matrix (0-7)
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// hardware cursor registers
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wire [10:0] cursor;
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reg [5:0] h_cursor;
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reg [4:0] v_cursor;
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// vram indexing registers
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reg [5:0] vram_h_addr;
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reg [4:0] vram_v_addr;
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reg [4:0] vram_start_addr;
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reg [4:0] vram_end_addr;
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wire [4:0] vram_clr_addr;
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// vram registers
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wire [10:0] vram_r_addr;
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reg [10:0] vram_w_addr;
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reg vram_w_en;
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reg [5:0] vram_din;
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wire [5:0] vram_dout;
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// font rom registers
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wire [5:0] font_char;
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wire [2:0] font_pixel;
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wire [4:0] font_line;
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wire font_out;
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// active region strobes
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wire h_active = (h_cnt >= hbp && h_cnt < hfp);
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wire v_active = (v_cnt >= vbp && v_cnt < vfp);
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// horizontal and vertical counters
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always @(posedge sys_clock or posedge reset) begin
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if (reset) begin
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h_cnt <= 10'd0;
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v_cnt <= 10'd0;
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v_dot <= 5'd0;
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end
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else
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if(pixel_clken) begin
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if (h_cnt < h_pixels)
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h_cnt <= h_cnt + 1;
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else begin
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// reset horizontal counters
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h_cnt <= 0;
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if (v_cnt < v_lines) begin
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v_cnt <= v_cnt + 1;
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if (v_active) begin
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v_dot <= v_dot + 1;
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if (v_dot == 5'd7)
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v_dot <= 0;
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end
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end
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else begin
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// reset vertical counters
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v_cnt <= 0;
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v_dot <= 0;
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end
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end
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end
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end
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assign h_dot = h_active ? h_cnt[2:0] : 0;
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//////////////////////////////////////////////////////////////////////////
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// Character ROM
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font_rom font_rom(
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.clk(sys_clock),
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.character(font_char),
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.pixel(font_pixel),
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.line(font_line),
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.out(font_out)
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);
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//////////////////////////////////////////////////////////////////////////
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// Video RAM
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display_ram display_ram(
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.clk(sys_clock),
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.read_addr(vram_r_addr),
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.write_addr(vram_w_addr),
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.r_en(h_active),
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.w_en(vram_w_en),
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.din(vram_din),
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.dout(vram_dout)
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);
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//////////////////////////////////////////////////////////////////////////
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// Video Signal Generation
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always @(posedge sys_clock or posedge reset) begin
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if (reset) begin
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vram_h_addr <= 0;
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vram_v_addr <= 0;
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end
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else
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if(pixel_clken) begin
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// start the pipeline for reading vram and font details
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// 3 pixel clock cycles early
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if (h_dot == 6)
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vram_h_addr <= vram_h_addr + 1;
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// advance to next row when last display line is reached for row
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if (v_dot == 7 && h_cnt == 0)
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vram_v_addr <= vram_v_addr + 1;
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// clear the address registers if we're not in visible area
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if (~h_active) vram_h_addr <= 0;
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if (~v_active) vram_v_addr <= vram_start_addr;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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// Cursor blinking.
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// On the real Apple-I it's made via a 555 configured to trigger 1.92 Hz
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localparam blink_max = 7457385; // 14318180/2/(1.92/2)
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localparam blink_thr = blink_max * 3/4; // ~3/4 duty cycle
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localparam blink_rewind = blink_thr - (455 * 262); // sets blinking 1 frame before cursor turns on
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reg [31:0] blink_cnt;
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wire cursor_on = blink_cnt > blink_thr;
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always @(posedge sys_clock or posedge reset)
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begin
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if (reset)
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blink_cnt <= 0;
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else
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if(pixel_clken) begin
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if(cpu_clken & w_en & ready) blink_cnt <= blink_rewind; // when a char is received, blinking is turned off briefly
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else if(blink_cnt > blink_max) blink_cnt <= 0;
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else blink_cnt <= blink_cnt + 1;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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// Pipeline and VGA signals
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// vram to font rom to display pipeline assignments
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assign cursor = {v_cursor, h_cursor};
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assign vram_r_addr = {vram_v_addr, vram_h_addr};
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wire [5:0] cursor_character = cursor_on ? 6'd0 : 6'd32; // "@" or space
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assign font_char = (vram_r_addr != cursor) ? vram_dout : cursor_character;
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assign font_pixel = h_dot;
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assign font_line = v_dot * 2 + 4;
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wire cross_talk_artifact = (h_active & v_active) && v_dot == 0 && h_dot == 0;
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wire [5:0] pixel_out = { font_out, font_out, font_out, font_out, font_out | cross_talk_artifact, font_out };
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// vga signals out to monitor
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assign vga_red = (h_active & v_active) ? pixel_out : 6'b0;
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assign vga_grn = (h_active & v_active) ? pixel_out : 6'b0;
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assign vga_blu = (h_active & v_active) ? pixel_out : 6'b0;
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assign vga_h_sync = (h_cnt < h_pulse) ? 0 : 1;
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assign vga_v_sync = (v_cnt < v_pulse) ? 0 : 1;
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//////////////////////////////////////////////////////////////////////////
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// CPU control and hardware cursor
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assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]};
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always @(posedge sys_clock or posedge reset)
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begin
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if (reset) begin
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h_cursor <= 6'd0;
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v_cursor <= 5'd0;
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vram_start_addr <= 5'd0;
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vram_end_addr <= 5'd24;
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ready <= 0;
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end
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else
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if(pixel_clken) begin
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vram_w_en <= 0;
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// accepts a new character only at the start of each frame
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if(v_cnt == 0 && h_cnt == 0)
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ready <= 1;
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if(clr_screen) begin
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// return to top of screen
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h_cursor <= 6'd0;
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v_cursor <= 5'd0;
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vram_start_addr <= 5'd0;
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vram_end_addr <= 5'd24;
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// clear the screen
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vram_w_addr <= {vram_v_addr, vram_h_addr};
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vram_din <= 6'd32;
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vram_w_en <= 1;
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end
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else begin
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// cursor overflow handling
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if (h_cursor == 6'd40) begin
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h_cursor <= 6'd0;
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v_cursor <= v_cursor + 'd1;
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end
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if (v_cursor == vram_end_addr) begin
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vram_start_addr <= vram_start_addr + 'd1;
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vram_end_addr <= vram_end_addr + 'd1;
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end
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// address low == TX register
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if (address == 1'b0) begin
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if (cpu_clken & w_en & ready) begin
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// incoming character
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ready <= 0;
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dout[6:0] <= din[6:0];
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if(din[6:0]=='h0D) begin
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// handle carriage return
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h_cursor <= 0;
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v_cursor <= v_cursor + 'd1;
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end
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else if(din[6:0] < 32) begin
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// 0-31 non printable characters, do nothing
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end
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else begin
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vram_w_addr <= cursor;
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vram_din <= {~din[6], din[4:0]};
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vram_w_en <= 1;
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h_cursor <= h_cursor + 1;
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end
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end
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end
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else begin
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vram_w_addr <= {vram_clr_addr, vram_h_addr};
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vram_din <= 6'd32;
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vram_w_en <= 1;
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end
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end
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end
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end
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endmodule
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