46 lines
1.5 KiB
VHDL
46 lines
1.5 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Q_table is
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port (
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Q_reg : in unsigned(3 downto 0);
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filter_q : out signed(17 downto 0) );
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end Q_table;
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architecture Gideon of Q_table is
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type t_18_bit_array is array(natural range <>) of signed(17 downto 0);
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function create_factors(max_Q: real) return t_18_bit_array is
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constant critical : real := 0.70710678; -- no resonance at 0.5*sqrt(2)
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variable q_step : real;
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variable q : real;
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variable scaled : real;
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variable ret : t_18_bit_array(0 to 15);
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begin
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q_step := (max_Q - critical) / 15.0; -- linear
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for i in 0 to 15 loop
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q := critical + (real(i) * q_step);
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scaled := 65536.0 / q;
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ret(i) := to_signed(integer(scaled), 18);
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end loop;
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return ret;
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end function;
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constant c_table : t_18_bit_array(0 to 15) := create_factors(1.8);
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begin
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filter_q <= c_table(to_integer(Q_reg));
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end Gideon;
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