221 lines
7.3 KiB
VHDL
221 lines
7.3 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.sid_debug_pkg.all;
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-- LUT: 195, FF:68
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entity adsr_multi is
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generic (
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g_num_voices : integer := 8 );
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port (
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clock : in std_logic;
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reset : in std_logic;
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voice_i : in unsigned(3 downto 0);
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enable_i : in std_logic;
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voice_o : out unsigned(3 downto 0);
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enable_o : out std_logic;
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gate : in std_logic;
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attack : in std_logic_vector(3 downto 0);
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decay : in std_logic_vector(3 downto 0);
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sustain : in std_logic_vector(3 downto 0);
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release : in std_logic_vector(3 downto 0);
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env_state: out std_logic_vector(1 downto 0); -- for testing only
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env_out : out unsigned(7 downto 0) );
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end adsr_multi;
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-- 158 1 62 .. FF
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-- 45 2 35 .. 61
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-- 26 4 1C .. 34
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-- 13 8 0D .. 1B
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-- 6 16 07 .. 0C
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-- 7 30 00 .. 06
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architecture gideon of adsr_multi is
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type presc_array_t is array(natural range <>) of unsigned(15 downto 0);
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constant prescalers : presc_array_t(0 to 15) := (
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X"0008", X"001F", X"003E", X"005E",
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X"0094", X"00DB", X"010A", X"0138",
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X"0187", X"03D0", X"07A1", X"0C35",
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X"0F42", X"2DC7", X"4C4B", X"7A12" );
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signal enveloppe : unsigned(7 downto 0) := (others => '0');
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signal state : unsigned(1 downto 0) := (others => '0');
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constant st_release : unsigned(1 downto 0) := "00";
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constant st_attack : unsigned(1 downto 0) := "01";
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constant st_decay : unsigned(1 downto 0) := "11";
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type state_array_t is array(natural range <>) of unsigned(29 downto 0);
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signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0'));
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begin
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env_out <= enveloppe;
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env_state <= std_logic_vector(state);
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-- FF-5E 01
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-- 5D-37 02
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-- 36-1B 04
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-- 1A-0F 08
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-- 0E-07 10
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-- 06-01 1E
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process(clock)
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function logarithmic(lev: unsigned(7 downto 0)) return unsigned is
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variable res : unsigned(4 downto 0);
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begin
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if lev = X"00" then
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res := "00000"; -- prescaler off
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elsif lev < X"07" then
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res := "11101"; -- 1E-1
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elsif lev < X"0F" then
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res := "01111"; -- 10-1
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elsif lev < X"1B" then
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res := "00111"; -- 08-1
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elsif lev < X"37" then
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res := "00011"; -- 04-1
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elsif lev < X"5E" then
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res := "00001"; -- 02-1
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else
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res := "00000"; -- 01-1
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end if;
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return res;
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end function logarithmic;
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variable presc_select : integer range 0 to 15;
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variable cur_state : unsigned(1 downto 0);
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variable cur_env : unsigned(7 downto 0);
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variable cur_pre15 : unsigned(14 downto 0);
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variable cur_pre5 : unsigned(4 downto 0);
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variable next_state : unsigned(1 downto 0);
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variable next_env : unsigned(7 downto 0);
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variable next_pre15 : unsigned(14 downto 0);
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variable next_pre5 : unsigned(4 downto 0);
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variable presc_val : unsigned(14 downto 0);
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variable log_div : unsigned(4 downto 0);
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variable do_count_15 : std_logic;
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variable do_count_5 : std_logic;
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begin
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if rising_edge(clock) then
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cur_state := state_array(0)(1 downto 0);
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cur_env := state_array(0)(9 downto 2);
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cur_pre15 := state_array(0)(24 downto 10);
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cur_pre5 := state_array(0)(29 downto 25);
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voice_o <= voice_i;
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enable_o <= enable_i;
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next_state := cur_state;
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next_env := cur_env;
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next_pre15 := cur_pre15;
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next_pre5 := cur_pre5;
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-- PRESCALER LOGIC, output: do_count --
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-- 15 bit prescaler select --
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case cur_state is
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when st_attack =>
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presc_select := to_integer(unsigned(attack));
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when st_decay =>
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presc_select := to_integer(unsigned(decay));
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when others => -- includes release and idle
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presc_select := to_integer(unsigned(release));
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end case;
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presc_val := prescalers(presc_select)(14 downto 0);
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-- 15 bit prescaler counter --
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do_count_15 := '0';
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if cur_pre15 = presc_val then
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next_pre15 := (others => '0');
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do_count_15 := '1';
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else
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next_pre15 := cur_pre15 + 1;
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end if;
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-- 5 bit prescaler --
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log_div := logarithmic(cur_env);
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do_count_5 := '0';
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if do_count_15='1' then
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if (cur_state = st_attack) or cur_pre5 = log_div then
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next_pre5 := "00000";
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do_count_5 := '1';
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else
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next_pre5 := cur_pre5 + 1;
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end if;
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end if;
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-- END PRESCALER LOGIC --
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case cur_state is
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when st_attack =>
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if gate = '0' then
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next_state := st_release;
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elsif cur_env = X"FF" then
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next_state := st_decay;
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end if;
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if do_count_15='1' then
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next_env := cur_env + 1;
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-- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!!
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-- next_state := st_decay;
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-- end if;
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end if;
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when st_decay =>
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if gate = '0' then
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next_state := st_release;
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end if;
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if do_count_15='1' and do_count_5='1' and
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std_logic_vector(cur_env) /= (sustain & sustain) and
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cur_env /= X"00" then
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next_env := cur_env - 1;
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end if;
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when st_release =>
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if gate = '1' then
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next_state := st_attack;
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end if;
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if do_count_15='1' and do_count_5='1' and
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cur_env /= X"00" then
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next_env := cur_env - 1;
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end if;
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when others =>
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next_state := st_release;
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end case;
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if enable_i='1' then
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state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1);
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state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state;
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enveloppe <= next_env;
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state <= next_state;
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end if;
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if reset='1' then
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state <= "00";
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enveloppe <= (others => '0');
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enable_o <= '0';
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end if;
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end if;
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end process;
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end gideon;
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