59 lines
1.5 KiB
VHDL
59 lines
1.5 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sid_ctrl is
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generic (
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g_num_voices : natural := 8 );
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port (
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clock : in std_logic;
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reset : in std_logic;
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start_iter : in std_logic;
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voice_osc : out unsigned(3 downto 0);
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enable_osc : out std_logic );
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end sid_ctrl;
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architecture gideon of sid_ctrl is
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signal voice_cnt : unsigned(3 downto 0);
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signal enable : std_logic;
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begin
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process(clock)
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begin
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if rising_edge(clock) then
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if reset='1' then
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voice_cnt <= X"0";
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enable <= '0';
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elsif start_iter='1' then
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voice_cnt <= X"0";
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enable <= '1';
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elsif voice_cnt = g_num_voices-1 then
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voice_cnt <= X"0";
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enable <= '0';
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elsif enable='1' then
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voice_cnt <= voice_cnt + 1;
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enable <= '1';
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end if;
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end if;
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end process;
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voice_osc <= voice_cnt;
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enable_osc <= enable;
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end gideon;
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