116 lines
3.5 KiB
VHDL
116 lines
3.5 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.my_math_pkg.all;
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entity sid_mixer is
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port (
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clock : in std_logic;
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reset : in std_logic;
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valid_in : in std_logic := '0';
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direct_out : in signed(17 downto 0);
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high_pass : in signed(17 downto 0);
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band_pass : in signed(17 downto 0);
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low_pass : in signed(17 downto 0);
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filter_hp : in std_logic;
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filter_bp : in std_logic;
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filter_lp : in std_logic;
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volume : in unsigned(3 downto 0);
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mixed_out : out signed(17 downto 0);
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valid_out : out std_logic );
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end sid_mixer;
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architecture arith of sid_mixer is
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signal mix_i : signed(17 downto 0);
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signal mix_uns : unsigned(16 downto 0);
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signal vol_uns : unsigned(16 downto 0);
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signal vol_s : signed(16 downto 0);
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signal state : integer range 0 to 7;
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signal p_mul : unsigned(33 downto 0);
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signal p_mul_s : signed(34 downto 0);
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type t_volume_lut is array(natural range <>) of unsigned(15 downto 0);
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constant c_volume_lut : t_volume_lut(0 to 15) := (
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X"0000", X"0EEF", X"1DDE", X"2CCD", X"3BBC", X"4AAA", X"5999", X"6888",
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X"7777", X"8666", X"9555", X"A444", X"B333", X"C221", X"D110", X"DFFF" );
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begin
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process(clock)
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variable mix_total : signed(17 downto 0);
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begin
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if rising_edge(clock) then
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valid_out <= '0';
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state <= state + 1;
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case state is
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when 0 =>
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if valid_in = '1' then
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mix_i <= sum_limit(direct_out, to_signed(16384, 18));
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else
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state <= 0;
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end if;
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when 1 =>
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if filter_hp='1' then
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mix_i <= sum_limit(mix_i, high_pass);
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end if;
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when 2 =>
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if filter_bp='1' then
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mix_i <= sum_limit(mix_i, band_pass);
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end if;
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when 3 =>
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if filter_lp='1' then
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mix_i <= sum_limit(mix_i, low_pass);
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end if;
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when 4 =>
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-- p_mul <= mix_uns * vol_uns;
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p_mul_s <= mix_i * vol_s;
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valid_out <= '1';
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state <= 0;
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when others =>
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state <= 0;
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end case;
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-- mix_total := not(p_mul(32)) & signed(p_mul(31 downto 15));
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-- mixed_out <= mix_total; -- + to_signed(16384, 18);
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mixed_out <= p_mul_s(33 downto 16);
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if reset='1' then
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mix_i <= (others => '0');
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state <= 0;
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end if;
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end if;
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end process;
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-- vol_uns <= "0" & volume & volume & volume & volume;
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-- vol_uns <= '0' & c_volume_lut(to_integer(volume));
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-- mix_uns <= not mix_i(17) & unsigned(mix_i(16 downto 1));
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vol_s <= '0' & signed(c_volume_lut(to_integer(volume)));
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end arith;
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