412 lines
9.4 KiB
VHDL
412 lines
9.4 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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entity sid_top is
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generic (
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g_filter_div : natural := 141; --for 32 MHz (221; -- for 50 MHz)
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g_num_voices : natural := 3 );
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port (
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clock : in std_logic;
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reset : in std_logic;
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addr : in unsigned(7 downto 0);
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wren : in std_logic;
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wdata : in std_logic_vector(7 downto 0);
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rdata : out std_logic_vector(7 downto 0);
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potx : in std_logic_vector(7 downto 0);
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poty : in std_logic_vector(7 downto 0);
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comb_wave_l : in std_logic := '0';
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comb_wave_r : in std_logic := '0';
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start_iter : in std_logic;
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sample_left : out signed(17 downto 0);
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sample_right : out signed(17 downto 0);
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extfilter_en : in std_logic
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);
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end sid_top;
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architecture structural of sid_top is
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-- Voice index in pipe
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signal voice_osc : unsigned(3 downto 0);
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signal voice_wave : unsigned(3 downto 0);
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signal voice_mul : unsigned(3 downto 0);
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signal enable_osc : std_logic;
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signal enable_wave : std_logic;
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signal enable_mul : std_logic;
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-- Oscillator parameters
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signal freq : unsigned(15 downto 0);
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signal test : std_logic;
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signal sync : std_logic;
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-- Wave map parameters
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signal msb_other : std_logic;
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signal comb_mode : std_logic;
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signal ring_mod : std_logic;
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signal wave_sel : std_logic_vector(3 downto 0);
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signal sq_width : unsigned(11 downto 0);
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-- ADSR parameters
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signal gate : std_logic;
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signal attack : std_logic_vector(3 downto 0);
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signal decay : std_logic_vector(3 downto 0);
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signal sustain : std_logic_vector(3 downto 0);
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signal release : std_logic_vector(3 downto 0);
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-- Filter enable
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signal filter_en : std_logic;
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-- globals
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signal volume_l : unsigned(3 downto 0);
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signal filter_co_l : unsigned(10 downto 0);
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signal filter_res_l : unsigned(3 downto 0);
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signal filter_hp_l : std_logic;
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signal filter_bp_l : std_logic;
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signal filter_lp_l : std_logic;
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signal voice3_off_l : std_logic;
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signal volume_r : unsigned(3 downto 0);
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signal filter_co_r : unsigned(10 downto 0);
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signal filter_res_r : unsigned(3 downto 0);
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signal filter_hp_r : std_logic;
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signal filter_bp_r : std_logic;
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signal filter_lp_r : std_logic;
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signal voice3_off_r : std_logic;
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-- readback
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signal osc3 : std_logic_vector(7 downto 0);
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signal env3 : std_logic_vector(7 downto 0);
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-- intermediate flags and signals
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signal test_wave : std_logic;
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signal osc_val : unsigned(23 downto 0);
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signal carry_20 : std_logic;
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signal enveloppe : unsigned(7 downto 0);
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signal waveform : unsigned(11 downto 0);
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signal valid_sum : std_logic;
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signal valid_filt : std_logic;
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signal valid_mix : std_logic;
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signal filter_out_l: signed(17 downto 0) := (others => '0');
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signal direct_out_l: signed(17 downto 0) := (others => '0');
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signal high_pass_l : signed(17 downto 0) := (others => '0');
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signal band_pass_l : signed(17 downto 0) := (others => '0');
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signal low_pass_l : signed(17 downto 0) := (others => '0');
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signal mixed_out_l : signed(17 downto 0) := (others => '0');
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signal filter_out_r: signed(17 downto 0) := (others => '0');
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signal direct_out_r: signed(17 downto 0) := (others => '0');
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signal high_pass_r : signed(17 downto 0) := (others => '0');
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signal band_pass_r : signed(17 downto 0) := (others => '0');
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signal low_pass_r : signed(17 downto 0) := (others => '0');
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signal mixed_out_r : signed(17 downto 0) := (others => '0');
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begin
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i_regs: entity work.sid_regs
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port map
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(
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clock => clock,
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reset => reset,
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addr => addr,
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wren => wren,
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wdata => wdata,
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rdata => rdata,
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potx => potx,
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poty => poty,
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comb_wave_l => comb_wave_l,
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comb_wave_r => comb_wave_r,
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voice_osc => voice_osc,
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voice_wave => voice_wave,
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voice_adsr => voice_wave,
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voice_mul => voice_mul,
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-- Oscillator parameters
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freq => freq,
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test => test,
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sync => sync,
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-- Wave map parameters
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comb_mode => comb_mode,
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ring_mod => ring_mod,
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wave_sel => wave_sel,
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sq_width => sq_width,
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-- ADSR parameters
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gate => gate,
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attack => attack,
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decay => decay,
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sustain => sustain,
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release => release,
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-- mixer parameters
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filter_en => filter_en,
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-- globals
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volume_l => volume_l,
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filter_co_l => filter_co_l,
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filter_res_l=> filter_res_l,
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filter_ex_l => open,
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filter_hp_l => filter_hp_l,
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filter_bp_l => filter_bp_l,
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filter_lp_l => filter_lp_l,
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voice3_off_l=> voice3_off_l,
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volume_r => volume_r,
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filter_co_r => filter_co_r,
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filter_res_r=> filter_res_r,
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filter_ex_r => open,
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filter_hp_r => filter_hp_r,
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filter_bp_r => filter_bp_r,
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filter_lp_r => filter_lp_r,
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voice3_off_r=> voice3_off_r,
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-- readback
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osc3 => osc3,
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env3 => env3
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);
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i_ctrl: entity work.sid_ctrl
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generic map
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(
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g_num_voices => g_num_voices
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)
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port map
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(
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clock => clock,
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reset => reset,
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start_iter => start_iter,
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voice_osc => voice_osc,
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enable_osc => enable_osc
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);
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osc: entity work.oscillator
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generic map
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(
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g_num_voices
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)
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port map
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(
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clock => clock,
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reset => reset,
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voice_i => voice_osc,
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voice_o => voice_wave,
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enable_i => enable_osc,
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enable_o => enable_wave,
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freq => freq,
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test => test,
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sync => sync,
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osc_val => osc_val,
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test_o => test_wave,
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carry_20 => carry_20,
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msb_other => msb_other
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);
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wmap: entity work.wave_map
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generic map
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(
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g_num_voices => g_num_voices,
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g_sample_bits => 12
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)
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port map
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(
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clock => clock,
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reset => reset,
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test => test_wave,
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osc_val => osc_val,
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carry_20 => carry_20,
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msb_other => msb_other,
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voice_i => voice_wave,
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enable_i => enable_wave,
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comb_mode => comb_mode,
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wave_sel => wave_sel,
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ring_mod => ring_mod,
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sq_width => sq_width,
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voice_o => voice_mul,
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enable_o => enable_mul,
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wave_out => waveform
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);
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adsr: entity work.adsr_multi
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generic map
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(
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g_num_voices => g_num_voices
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)
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port map
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(
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clock => clock,
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reset => reset,
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voice_i => voice_wave,
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enable_i => enable_wave,
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voice_o => open,
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enable_o => open,
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gate => gate,
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attack => attack,
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decay => decay,
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sustain => sustain,
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release => release,
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env_state=> open, -- for testing only
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env_out => enveloppe
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);
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sum: entity work.mult_acc(signed_wave)
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port map
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(
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clock => clock,
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reset => reset,
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voice_i => voice_mul,
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enable_i => enable_mul,
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voice3_off_l=> voice3_off_l,
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voice3_off_r=> voice3_off_r,
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enveloppe => enveloppe,
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waveform => waveform,
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filter_en => filter_en,
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osc3 => osc3,
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env3 => env3,
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valid_out => valid_sum,
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filter_out_L => filter_out_L,
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filter_out_R => filter_out_R,
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direct_out_L => direct_out_L,
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direct_out_R => direct_out_R
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);
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i_filt_left: entity work.sid_filter
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generic map
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(
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g_divider => g_filter_div
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)
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port map
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(
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clock => clock,
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reset => reset,
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enable => extfilter_en,
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filt_co => filter_co_l,
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filt_res => filter_res_l,
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valid_in => valid_sum,
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input => filter_out_L,
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high_pass => high_pass_L,
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band_pass => band_pass_L,
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low_pass => low_pass_L,
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error_out => open,
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valid_out => valid_filt
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);
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mix: entity work.sid_mixer
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port map
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(
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clock => clock,
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reset => reset,
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valid_in => valid_filt,
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direct_out => direct_out_L,
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high_pass => high_pass_L,
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band_pass => band_pass_L,
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low_pass => low_pass_L,
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filter_hp => filter_hp_l,
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filter_bp => filter_bp_l,
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filter_lp => filter_lp_l,
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volume => volume_l,
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mixed_out => mixed_out_L,
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valid_out => open
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);
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i_filt_right: entity work.sid_filter
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generic map
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(
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g_divider => g_filter_div
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)
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port map
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(
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clock => clock,
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reset => reset,
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enable => extfilter_en,
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filt_co => filter_co_r,
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filt_res => filter_res_r,
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valid_in => valid_sum,
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input => filter_out_R,
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high_pass => high_pass_R,
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band_pass => band_pass_R,
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low_pass => low_pass_R,
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error_out => open,
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valid_out => open
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);
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mix_right: entity work.sid_mixer
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port map
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(
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clock => clock,
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reset => reset,
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valid_in => valid_filt,
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direct_out => direct_out_R,
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high_pass => high_pass_R,
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band_pass => band_pass_R,
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low_pass => low_pass_R,
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filter_hp => filter_hp_r,
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filter_bp => filter_bp_r,
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filter_lp => filter_lp_r,
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volume => volume_r,
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mixed_out => mixed_out_R,
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valid_out => open
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);
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sample_left <= mixed_out_L;
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sample_right <= mixed_out_R;
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end structural;
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